Hi,
We are using Cortex-M0+ embedded in our hardware design and would like to simulate the firmware along with the micro and the rest of the hardware using Synopsys Verdi HW/SW Debugger which works together with Eclipse. The debugger requires an .fsdb file which can be generated from the .elf file and cpu.log file. Both, I assume can be generated during compilation. Currently only the .elf file is being generated when using this command:
/tools/compilers/arm-gcc-6.3/armv7-rpi2-linux-gnueabihf/bin/armv7-rpi2-linux-gnueabihf-gcc
Is there a specific compile option to enable "cpu.log" file generation? I do not know how ARM referrers to this file, but the content of it should be something like: R CPSR 000001d3 10245 ns IE 00000000 [e59ff018] MR4 00000020 0000003c 10975 ns IE 0000003c [ea000011] 11445 ns IE 00000088 [e3a00000] R R0 00000000 11445 ns IE 0000008c [e3a01000] R R1 00000000 11445 ns IE 00000090 [e3a02000] R R2 00000000
R CPSR 000001d3
10245 ns IE 00000000 [e59ff018]
MR4 00000020 0000003c
10975 ns IE 0000003c [ea000011]
11445 ns IE 00000088 [e3a00000]
R R0 00000000
11445 ns IE 0000008c [e3a01000]
R R1 00000000
11445 ns IE 00000090 [e3a02000]
R R2 00000000
Thank you for your help.
Hi Ronan,
I thought so too, but I was mislead by Synopsys User guide saying "The CPU log file generated from the design (executing embedded C code) is used as an input by Verdi HW/SW Debug Solution. For details on generating this file, refer to your CPU vendor instructions."