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Does GCC really support automatic vectorization for NEON technology?

Cyberman Wu over 10 years ago

There are two development articles metioned it that GCC can do it:

ntroducing NEON

NEON Support in Compilation Tools

But I tested code snap in these docs with GCC compling options but the generated assembly code

doesn't use any neon instruction.

Top replies

Peter Harris over 10 years ago in reply to Cyberman Wu +1 verified

Glad you got it working =) Hint of loop number like (len & ~3) is not required, In library code where "len" cannot be determined this helps the compiler avoid unneeded code. Normally it will still vectorize...

Parents

0 Cyberman Wu over 10 years ago in reply to Peter Harris

It should be what you said, but the real compiling result is almost the same.

1) Without the hint of 'len & ~3'

int accumulate(int * __attribute__ ((aligned (16))) c, int len)

{

int i, retval;

for(i=0, retval = 0; i < len; i++) {

retval += c[i];

}

return retval;

}

Compling output:

	.align	2
	.global	accumulate
	.type	accumulate, %function

accumulate:

	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
	cmp	r1, #0
	stmfd	sp!, {r4, r5, r6, r7}
	ble	.L14
	ands	r2, r0, #4
	mvnne	r2, #0
	and	r2, r2, #3
	cmp	r2, r1
	movcs	r2, r1
	cmp	r1, #6
	movls	r2, r1
	bhi	.L28

.L3:

	cmp	r2, #1
	ldr	r3, [r0]
	movls	ip, #1
	bls	.L5
	ldr	ip, [r0, #4]
	cmp	r2, #2
	add	r3, r3, ip
	movls	ip, #2
	bls	.L5
	ldr	ip, [r0, #8]
	cmp	r2, #3
	add	r3, r3, ip
	movls	ip, #3
	bls	.L5
	ldr	ip, [r0, #12]
	cmp	r2, #4
	add	r3, r3, ip
	movls	ip, #4
	bls	.L5
	cmp	r2, #5
	ldr	ip, [r0, #16]
	ldrhi	r4, [r0, #20]
	add	r3, r3, ip
	addhi	r3, r3, r4
	movls	ip, #5
	movhi	ip, #6

.L5:

	cmp	r1, r2
	beq	.L2
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	beq	.L7

.L29:

	add	r2, r0, r2, asl #2
	mov	r4, #0
	vmov.i32	q8, #0 @ v4si

.L13:

	add	r4, r4, #1
	vld1.64	{d18-d19}, [r2:64]!
	cmp	r5, r4
	vadd.i32	q8, q8, q9
	bhi	.L13
	vadd.i32	d16, d16, d17
	vmov.i32	q9, #0 @ v4si
	vpadd.i32	d18, d16, d16
	vmov.32	r2, d18[0]
	cmp	r6, r7
	add	ip, ip, r7
	add	r3, r3, r2
	beq	.L2

.L7:

	ldr	r4, [r0, ip, asl #2]
	add	r2, ip, #1
	cmp	r1, r2
	add	r3, r3, r4
	ble	.L2
	ldr	r2, [r0, r2, asl #2]
	add	ip, ip, #2
	cmp	r1, ip
	add	r3, r3, r2
	ldrgt	r2, [r0, ip, asl #2]
	addgt	r3, r3, r2

.L2:

	mov	r0, r3
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

.L28:

	cmp	r2, #0
	moveq	r3, r2
	moveq	ip, r2
	bne	.L3
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	bne	.L29
	b	.L7

.L14:

	mov	r3, #0
	b	.L2
	.size	accumulate, .-accumulate

2) With the hint of 'len & ~3'

int accumulate(int * __attribute__ ((aligned (16))) c, int len)

{

int i, retval;

for(i=0, retval = 0; i < (len & ~3) ; i++) {

retval += c[i];

}

return retval;

}

Compling result:

	.align	2
	.global	accumulate
	.type	accumulate, %function

accumulate:

	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
	bic	r1, r1, #3
	cmp	r1, #0
	stmfd	sp!, {r4, r5, r6, r7}
	ble	.L14
	ands	r2, r0, #4
	mvnne	r2, #0
	and	r2, r2, #3
	cmp	r2, r1
	movcs	r2, r1
	cmp	r1, #6
	movls	r2, r1
	bhi	.L28

.L3:

	cmp	r2, #1
	ldr	r3, [r0]
	movls	ip, #1
	bls	.L5
	ldr	ip, [r0, #4]
	cmp	r2, #2
	add	r3, r3, ip
	movls	ip, #2
	bls	.L5
	ldr	ip, [r0, #8]
	cmp	r2, #3
	add	r3, r3, ip
	movls	ip, #3
	bls	.L5
	ldr	ip, [r0, #12]
	cmp	r2, #4
	add	r3, r3, ip
	movls	ip, #4
	bls	.L5
	cmp	r2, #5
	ldr	ip, [r0, #16]
	ldrhi	r4, [r0, #20]
	add	r3, r3, ip
	addhi	r3, r3, r4
	movls	ip, #5
	movhi	ip, #6

.L5:

	cmp	r1, r2
	beq	.L2
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	beq	.L7

.L29:

	add	r2, r0, r2, asl #2
	mov	r4, #0
	vmov.i32	q8, #0 @ v4si

.L13:

	add	r4, r4, #1
	vld1.64	{d18-d19}, [r2:64]!
	cmp	r5, r4
	vadd.i32	q8, q8, q9
	bhi	.L13
	vadd.i32	d16, d16, d17
	vmov.i32	q9, #0 @ v4si
	vpadd.i32	d18, d16, d16
	vmov.32	r2, d18[0]
	cmp	r6, r7
	add	ip, ip, r7
	add	r3, r3, r2
	beq	.L2

.L7:

	ldr	r4, [r0, ip, asl #2]
	add	r2, ip, #1
	cmp	r2, r1
	add	r3, r3, r4
	bge	.L2
	ldr	r2, [r0, r2, asl #2]
	add	ip, ip, #2
	cmp	r1, ip
	add	r3, r3, r2
	ldrgt	r2, [r0, ip, asl #2]
	addgt	r3, r3, r2

.L2:

	mov	r0, r3
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

.L28:

	cmp	r2, #0
	moveq	r3, r2
	moveq	ip, r2
	bne	.L3
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	bne	.L29
	b	.L7

.L14:

	mov	r3, #0
	b	.L2
	.size	accumulate, .-accumulate

The only different is that 'len & ~3' complied into a instruction 'bic r1, r1, #3', nothing else.

Reply

0 Cyberman Wu over 10 years ago in reply to Peter Harris

It should be what you said, but the real compiling result is almost the same.

1) Without the hint of 'len & ~3'

int accumulate(int * __attribute__ ((aligned (16))) c, int len)

{

int i, retval;

for(i=0, retval = 0; i < len; i++) {

retval += c[i];

}

return retval;

}

Compling output:

	.align	2
	.global	accumulate
	.type	accumulate, %function

accumulate:

	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
	cmp	r1, #0
	stmfd	sp!, {r4, r5, r6, r7}
	ble	.L14
	ands	r2, r0, #4
	mvnne	r2, #0
	and	r2, r2, #3
	cmp	r2, r1
	movcs	r2, r1
	cmp	r1, #6
	movls	r2, r1
	bhi	.L28

.L3:

	cmp	r2, #1
	ldr	r3, [r0]
	movls	ip, #1
	bls	.L5
	ldr	ip, [r0, #4]
	cmp	r2, #2
	add	r3, r3, ip
	movls	ip, #2
	bls	.L5
	ldr	ip, [r0, #8]
	cmp	r2, #3
	add	r3, r3, ip
	movls	ip, #3
	bls	.L5
	ldr	ip, [r0, #12]
	cmp	r2, #4
	add	r3, r3, ip
	movls	ip, #4
	bls	.L5
	cmp	r2, #5
	ldr	ip, [r0, #16]
	ldrhi	r4, [r0, #20]
	add	r3, r3, ip
	addhi	r3, r3, r4
	movls	ip, #5
	movhi	ip, #6

.L5:

	cmp	r1, r2
	beq	.L2
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	beq	.L7

.L29:

	add	r2, r0, r2, asl #2
	mov	r4, #0
	vmov.i32	q8, #0 @ v4si

.L13:

	add	r4, r4, #1
	vld1.64	{d18-d19}, [r2:64]!
	cmp	r5, r4
	vadd.i32	q8, q8, q9
	bhi	.L13
	vadd.i32	d16, d16, d17
	vmov.i32	q9, #0 @ v4si
	vpadd.i32	d18, d16, d16
	vmov.32	r2, d18[0]
	cmp	r6, r7
	add	ip, ip, r7
	add	r3, r3, r2
	beq	.L2

.L7:

	ldr	r4, [r0, ip, asl #2]
	add	r2, ip, #1
	cmp	r1, r2
	add	r3, r3, r4
	ble	.L2
	ldr	r2, [r0, r2, asl #2]
	add	ip, ip, #2
	cmp	r1, ip
	add	r3, r3, r2
	ldrgt	r2, [r0, ip, asl #2]
	addgt	r3, r3, r2

.L2:

	mov	r0, r3
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

.L28:

	cmp	r2, #0
	moveq	r3, r2
	moveq	ip, r2
	bne	.L3
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	bne	.L29
	b	.L7

.L14:

	mov	r3, #0
	b	.L2
	.size	accumulate, .-accumulate

2) With the hint of 'len & ~3'

int accumulate(int * __attribute__ ((aligned (16))) c, int len)

{

int i, retval;

for(i=0, retval = 0; i < (len & ~3) ; i++) {

retval += c[i];

}

return retval;

}

Compling result:

	.align	2
	.global	accumulate
	.type	accumulate, %function

accumulate:

	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
	bic	r1, r1, #3
	cmp	r1, #0
	stmfd	sp!, {r4, r5, r6, r7}
	ble	.L14
	ands	r2, r0, #4
	mvnne	r2, #0
	and	r2, r2, #3
	cmp	r2, r1
	movcs	r2, r1
	cmp	r1, #6
	movls	r2, r1
	bhi	.L28

.L3:

	cmp	r2, #1
	ldr	r3, [r0]
	movls	ip, #1
	bls	.L5
	ldr	ip, [r0, #4]
	cmp	r2, #2
	add	r3, r3, ip
	movls	ip, #2
	bls	.L5
	ldr	ip, [r0, #8]
	cmp	r2, #3
	add	r3, r3, ip
	movls	ip, #3
	bls	.L5
	ldr	ip, [r0, #12]
	cmp	r2, #4
	add	r3, r3, ip
	movls	ip, #4
	bls	.L5
	cmp	r2, #5
	ldr	ip, [r0, #16]
	ldrhi	r4, [r0, #20]
	add	r3, r3, ip
	addhi	r3, r3, r4
	movls	ip, #5
	movhi	ip, #6

.L5:

	cmp	r1, r2
	beq	.L2
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	beq	.L7

.L29:

	add	r2, r0, r2, asl #2
	mov	r4, #0
	vmov.i32	q8, #0 @ v4si

.L13:

	add	r4, r4, #1
	vld1.64	{d18-d19}, [r2:64]!
	cmp	r5, r4
	vadd.i32	q8, q8, q9
	bhi	.L13
	vadd.i32	d16, d16, d17
	vmov.i32	q9, #0 @ v4si
	vpadd.i32	d18, d16, d16
	vmov.32	r2, d18[0]
	cmp	r6, r7
	add	ip, ip, r7
	add	r3, r3, r2
	beq	.L2

.L7:

	ldr	r4, [r0, ip, asl #2]
	add	r2, ip, #1
	cmp	r2, r1
	add	r3, r3, r4
	bge	.L2
	ldr	r2, [r0, r2, asl #2]
	add	ip, ip, #2
	cmp	r1, ip
	add	r3, r3, r2
	ldrgt	r2, [r0, ip, asl #2]
	addgt	r3, r3, r2

.L2:

	mov	r0, r3
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

.L28:

	cmp	r2, #0
	moveq	r3, r2
	moveq	ip, r2
	bne	.L3
	rsb	r6, r2, r1
	mov	r5, r6, lsr #2
	movs	r7, r5, asl #2
	bne	.L29
	b	.L7

.L14:

	mov	r3, #0
	b	.L2
	.size	accumulate, .-accumulate

The only different is that 'len & ~3' complied into a instruction 'bic r1, r1, #3', nothing else.

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