I've noticed that arm gcc, when compiling code for Cortex-M0 (at least) seems to generate instructions:
adds r0, r2, #0
Where I'm pretty sure that it the same as:
movs r0, r2
In fact, I can disassemble a relatively substantial program and not find a single register/register "mov" or "movs" instruction (for r0..r7)
is there some reason for this?
MOVS r0, r2 is the same as LSLS r0, r2, 0 according to UAL syntax.
ADDS with zero was emitted by early Thumb-1 compilers, so GCC should ideally be updated as it makes disassembly harder to read.
Note it's generally best to report issues like this in the GCC bugzilla
Wilco