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ITM trace get from Cortex M4.

Akim-layachi DAINECHE
Note: This was originally posted on 16th March 2012 at http://forums.arm.com

Hello,

I am currently simulating behavior of Cortex M4 for trace. Very simple write throuhg the ITM to get the data trace port and then try to analyse it.
The purpose is to be able to compute the expected data each time we write a data through the ITM --> TPIU --> trace_port.
There is strange behavior I do not understand why in the code described below the first write to the ITM is not visible ...

thanks for your support

Akim



below you have the debug command file executed:


nRSTL                                             ; Assert Reset
DELAY 50000 ns
JTAG2SWD
READID 2BA01477                       ; Read SW ID Code

PWRUP                                           ; Powerup Product & Debug
TRACEMODE SYNC_PORT1
WRITE E000EDFC 01000000  ; DEMC_R : set TRCENA : otherwise, TPIU registers are not accessible
READ  E0040004 00000001    ; TPIU/CUR_PORTSIZE - read default config
READ  E0040300 00000008    ; TPIU/FORM_SR - read default config
READ  E0040304 00000102    ; TPIU/FORM_CR - read default config

WRITE E00400F0 00000000    ; TPIU/SPP : select SYNC PORT Mode
WRITE E0040004 00000001    ; TPIU/CPS : select PORT SIZE=1
WRITE E0001000 00000401    ; DWT/CR   : enable CYCCNTENA & SYNCTAP to generate sync triggers


WRITE E0000FB0 C5ACCE55    ; ITM/LOCK_ACC    : Unlock Write Access to ITM
WRITE E0000E80 00010005      ; ITM/TRACECTL    : Enable ITM with Sync enabled and ATB_ID=0x1
WRITE E0000E00 00000001      ; ITM/TRACEN      : Enable ITM Stimulus port0
WRITE E0000E40 00000001      ; ITM/TRACE_PRIV  : Unmask ITM Stimulus port7:0

WRITE E000EDF0 A05F0001    ; DHCS_R : Debug enabled
WRITE E000EDFC 01000001    ; DEMC_R : set a breakpoint on reset fetch with TRCENA

DELAY 1000 ns;
nRSTH                      ; release reset
DELAY 1000 ns;


WRITE E0042004 00000060    ; DBG_MCU_CR : assign SYNC TRACE I/Os for SIZE=1
                                   ; this outputs a sync packet of FF_FF_FF_7F

WRITE E0000000 DDCCBBAA    ; ITM/STIMU_PORT0 : Write DDCCBBAA    ; ====> this data ITM write not seen on trace !!!!!!!!!!!!!!!!!!!!!!!!!!!! ????
WRITE E0000000 AAAA5555       ; ITM/STIMU_PORT0 : Write AAAA5555


EXP_TRACE 7FFF7FFF7FFF7FFF8001000000000003; synchro packet
EXP_TRACE 03037FFF7FFF7FFF7FFF7FFF7FFF7FFF; synchro packet

EXP_TRACE 7FFF7FFF7FFF7FFF7FFFAAAA55540303 ; formatted trace of AAAA5555


WRITE E000EDF0 A05F0001    ; DHCS_R : Resume core execution (C_HALT=0)

; ===>                           ; software write STIMU_PORT0 with 0xFEDCBA98

EXP_TRACE 7FFF7FFF7FFF7FFF7FFFFEDCBA980303 ; formatted trace of 0xFEDCBA98 emitted by SW


CLOSE                      ; Close Debug
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