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How to avoid literal pools ?

Christophe Beausoleil
Note: This was originally posted on 19th January 2012 at http://forums.arm.com

Hello everyone,

I am using Cortex-R4F (TI TMS570), and I noticed that ARM C compiler often adds data in literal pools as in example below :
C code :
RTI_Re_TickFlag = 0;

ASM generated code :
000004  4c66              LDR      r4,|L1.416|
000006  2700              MOVS     r7,#0
...
    ENDP
    |L1.416|
         DCD      RTI_Re_TickFlag

My problem is that this constant is in the same section than the code, so the Cortex-R4 Harward architecture (separate data/instruction) is not used at its best.
It makes load/store unit (LSU) accesses interfere with prefetch unit (PFU) accesses.

So, can we make armcc (with optimization options or some directives...) not generate literal pools ?

Thanks

Best regards

Christophe
Parents
  • Note: This was originally posted on 20th January 2012 at http://forums.arm.com

    Hi,

    Thanks a lot for your answer.

    In fact, I should have said that TMS570 has no cache, and instructions come from flash through ATCM...

    So I really think that a solution might only come from some compiler options (forcing armcc to generate MOVW/MOVT sequence for loading a 32-bit address for example)

    Best regards

    Christophe
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  • Note: This was originally posted on 20th January 2012 at http://forums.arm.com

    Hi,

    Thanks a lot for your answer.

    In fact, I should have said that TMS570 has no cache, and instructions come from flash through ATCM...

    So I really think that a solution might only come from some compiler options (forcing armcc to generate MOVW/MOVT sequence for loading a 32-bit address for example)

    Best regards

    Christophe
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