• Locked Locked
  • Replies 8 replies
  • Subscribers 119 subscribers
  • Views 6917 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-A9 AMP

Clemens Fischer
Note: This was originally posted on 8th January 2012 at http://forums.arm.com

Hi,

I am currently examining amp for embedded devices.

Is it possible to boot two operating systems on an Cortex-A9 in amp mode?

The p2020 power processor is capable of amp and there is an  implementation in u-boot that makes it possible to boot two os in amp  mode. Is there a similar implementation for the Cortex-A9? And if  not, is it possible and what steps are necessary to implement amp with  the Cortex-A9 cpu using u-boot or a different boot loader?

 

Any information would be helpful.

Best regards

Clemens

Parents
  • Note: This was originally posted on 13th January 2012 at http://forums.arm.com

    Clemens,
    >>What other shared ressources are there that are visible to both OSes?

    Is there external cache controller on your H/W (PL310)? That would be another shared resource. Without any synchronization among OSs there will be limited set of PL310 cache maintenance operations. (Only atomic operation by physical address can be issued concurrently by both CPUs.)

    I understand that you would keep SCU (snoop control unit) off & all memory marked as not-shared. That will also prevent broadcasts of MMU maintenance operations on internal cache, TLB & branch predictor.
Reply
  • Note: This was originally posted on 13th January 2012 at http://forums.arm.com

    Clemens,
    >>What other shared ressources are there that are visible to both OSes?

    Is there external cache controller on your H/W (PL310)? That would be another shared resource. Without any synchronization among OSs there will be limited set of PL310 cache maintenance operations. (Only atomic operation by physical address can be issued concurrently by both CPUs.)

    I understand that you would keep SCU (snoop control unit) off & all memory marked as not-shared. That will also prevent broadcasts of MMU maintenance operations on internal cache, TLB & branch predictor.
Children
No data