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ARM7

sibin thomas
Note: This was originally posted on 28th November 2011 at http://forums.arm.com

i have a doubt related to ARM7TDMI.
in ARM7 architecture, the lower 5bits of CPSR register is MODE bits. we have 7modes in ARM7. when these 7 modes can be specified using 3bits, why 5bits have been set for mode selection?
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  • Arm Employee Badge
    Note: This was originally posted on 29th November 2011 at http://forums.arm.com

    Ok - I got curious...

    I know a couple of people who worked on early ARMs so asked them.  Very early ARMs had a 26-bit addressing scheme.  Bit 4 of the mode field originally determined whether you were in the 32-bit or 26-bit address scheme.  With the remaining bits (3:0) giving the mode (SVC, IRQ, etc...).
Reply
  • Arm Employee Badge
    Note: This was originally posted on 29th November 2011 at http://forums.arm.com

    Ok - I got curious...

    I know a couple of people who worked on early ARMs so asked them.  Very early ARMs had a 26-bit addressing scheme.  Bit 4 of the mode field originally determined whether you were in the 32-bit or 26-bit address scheme.  With the remaining bits (3:0) giving the mode (SVC, IRQ, etc...).
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