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Strange behaviour of cache

Note: This was originally posted on 19th November 2011 at http://forums.arm.com

Hi!

I have a Cortex a9 based board (currently only 1core is active another one is waiting for its time to come into a play).
My simplified caching routine in pseudo code looks like this:

Cache(set of parameters){
if(cache_op1)docache_op1();
if(cache_op2)docache_op2();
....
if(cache_opn)docache_opn();
}
An example of cache operation:
     mov r0, #0
     mcr p15, 0, r0, c7, c5, 0    ; I cache
     mcr p15, 0, r0, c7, c5, 6    ; BP
     DSB
     ISB
     bx   lr

The system hangs at some point...
But when I include a delay (several thousands of CPU cycles) it gets stable and works just fine:
Cache(set of parameters){
if(cache_op1)docache_op1();
if(cache_op2)docache_op2();
....
if(cache_opn)docache_opn();
Delay();
}
Disabling/enabling L2 cache doesn't seem to affect the system. So I think it is related to L1 cache.

Having delay in this function isn't acceptable because of performance issues and frankly speaking I don't know how long it should be delayed for in every particular case.
I suspect that some caching operations need time to complete. Is there a mechanism in ARM to ensure that caching operation is complete? I thought it was done by using the DSB instruction... But it is either ignored or used for a completely different purpose. If there is no such mechanism then how should it be handled? I mean if the program continues to execute while hardware operation is not finished. Otherwise I cannot explain my workaround with delay. Any ideas are welcome.

Thanks