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ARM stack alignment on exception entry

Lucas Tschuor
Note: This was originally posted on 8th November 2011 at http://forums.arm.com

Hello everybody,

The Application Binary Interface (ABI) for the ARM architecture requires that the stack must be eight-byte aligned on exception entry. The default stack alignment for Cortex-M3 is 4 byte and not 8 byte, why this ambiguity?

Why is it required anyway to configure the 8 byte stack alignment if it also works with 4 byte? Is there any reason?

Regards,
affonpign
  • Note: This was originally posted on 8th November 2011 at http://forums.arm.com

    Hello everybody,

    The Application Binary Interface (ABI) for the ARM architecture requires that the stack must be eight-byte aligned on exception entry. The default stack alignment for Cortex-M3 is 4 byte and not 8 byte, why this ambiguity?

    Why is it required anyway to configure the 8 byte stack alignment if it also works with 4 byte? Is there any reason?

    Regards,
    affonpign
  • Arm Employee Badge
    Note: This was originally posted on 8th November 2011 at http://forums.arm.com

    Starting in revision 1 of the Cortex-M3, the Configuration Control Register (address 0xE000ED14) has a STKALIGN control bit to control this behavior.  When this bit is set, the exception stack frame is double word aligned.

    From revision 2, this bit is set by default.

    There are some cases where double word stack alignment is essential - dependent on the application code.
    For example, when the interrupt handler or the functions that the interrupt handler accesses has pointer arithmetic that assumed the stack was double word aligned, the code might not work.

    If you are using  Cortex-M3 r1p0/r1p1, it is recommended to add
      SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    in the beginning of the application.
  • Note: This was originally posted on 8th November 2011 at http://forums.arm.com


    The default stack alignment for Cortex-M3 is 4 byte and not 8 byte, why this ambiguity?

    Erratum? in any case that was changed in r2p0.

    Why is it required anyway to configure the 8 byte stack alignment if it also works with 4 byte? Is there any reason?

    In current processors, there is no technical reason for this requirement. Up to ARMv5, LDRD/STRD were limited to 8byte aligned addresses, although that was probably not the only reason. But now that this requirement exists, we must be prepared for any (third-party) software relying on it in obscure ways, such as assuming that the 3 LSB of r13 must be 0 at function entry.
    If you are in full control of all code executing on a reasonably modern ARM processor the stack alignment could be reduced to 4.

    Regards
    Marcus