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ARMv6: "invalidate D-cache line" instruction doesn't work?

Zhanguo Li
Note: This was originally posted on 10th November 2011 at http://forums.arm.com

I am trying to test the "invalidate D-cache line" instruction of Freescale imx31/35 processor(ARMv6) and seems that it fails to work.

Below are my test pseudocode:
1. pBuf = malloc(xxx) /* alloc a write-back memory */
2. *(volatile char *)pBuf = 0; /* not cache  hit now and not write-allocate, so 0 is written to memory */
3. data = *(volatile char *)pBuf; /* read the date to cache */
4. *(char *)pBuf = 0xaa; /* write 0xaa to cache */
5. invalidate pBuf cache line; /* via mcr or mcrr instruction */
6. data = *(volatile char *)pBuf; /* read it again */
7.  data should not be 0xaa, otherwise the invalidate instruction does not work.

Note that my real test code are more strict than the pseudocode, and it works well in ARMv7 platform

So is there knowd issue for ARMv6 "invalidate D-cache line" instruction?

Thanks a lot!
-Jerry


Parents
  • Arm Employee Badge
    Note: This was originally posted on 18th November 2011 at http://forums.arm.com

    An invalidate causes the contents of the cache to be thrown away.  Which means that any dirty data (changes held in the cache, but not yet memory) are lost!

    If you want external memory to be updated you need to do a clean (or clean + invalidate).

    Other things to consider are barriers.  You may need to add a DSB between the cache command and the read/write of the address.  This is to ensure that they happen in order.  This is a side effect of a loosely ordered memory system.
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  • Arm Employee Badge
    Note: This was originally posted on 18th November 2011 at http://forums.arm.com

    An invalidate causes the contents of the cache to be thrown away.  Which means that any dirty data (changes held in the cache, but not yet memory) are lost!

    If you want external memory to be updated you need to do a clean (or clean + invalidate).

    Other things to consider are barriers.  You may need to add a DSB between the cache command and the read/write of the address.  This is to ensure that they happen in order.  This is a side effect of a loosely ordered memory system.
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