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APB confusion

Ganesh Kuppan
Note: This was originally posted on 1st September 2011 at http://forums.arm.com

Hi,

This may seem a very basic doubt. I have implemented APB peripheral on a Cortex M1 based ACTEL platform. I do 3 memory writes and 2 memory reads from the peripheral. The hardware peripheral takes 30 cycles to complete operation after 3 writes are completed to it. Then I do 2 reads.  So, I estimated the whole operation to be completed in around 40-45 cycles.  I read the AMBA specification and it says, APB peripherals require 2 cycles (address and data phase) to complete with no wait states. I have implemented AMBA 2.0 protocol, which does not have PREADY.  But each Load or Store to the peripheral is taking 40 cycles each and the total goes to around 200 cycles. How is this possible? Am I missing some knowledge about AMBA APB?

As my AHB2APB bridge is encrypted RTL, I cannot verify whether somehow this bridge is adding wait states (it can as it is a AHB slave).
Is the FPGA slow in responding and so AHB2APB is adding wait cycles?

Also, if APB transfers can also be done in 2 cycles, why not use the AHB for the same with one WAIT state?

My cortex M1, AHB2APB bridge and hardware peripheral are all working on same clock of 20MHz.

Would appreciate a detailed response.

Also to add, the counter used is again a APB peripheral . I write a value 1 to it, to start  counting. Then writes to the above HW peripheral start. After the whole write/read operation to above peripheral , I again write a 0 to counter to stop . Then I read the stored counter value. Because both the peripherals are APB and share the bridge any issues??
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  • Arm Employee Badge
    Note: This was originally posted on 5th September 2011 at http://forums.arm.com

    Yes, your question was a bit too device specific :)

    If you have implemented AMBA 2.0 APB, then as you have stated, there is no PREADY signal, so all transfers must take 2 PCLK cycles.

    So if you are seeing delays of 30-45 cycles, and the AHB and APB sides of the bridge are running 1:1 (with no CLKEN input stalling the APB clock), and these delays are not due to an earlier access to a non-APB device adding wait states of this sort of magnitude (which delays the APB transfer data phase starting), then something serious is wrong, and you would need to contact ACTEL if they are who supplied the IP.

    JD
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  • Arm Employee Badge
    Note: This was originally posted on 5th September 2011 at http://forums.arm.com

    Yes, your question was a bit too device specific :)

    If you have implemented AMBA 2.0 APB, then as you have stated, there is no PREADY signal, so all transfers must take 2 PCLK cycles.

    So if you are seeing delays of 30-45 cycles, and the AHB and APB sides of the bridge are running 1:1 (with no CLKEN input stalling the APB clock), and these delays are not due to an earlier access to a non-APB device adding wait states of this sort of magnitude (which delays the APB transfer data phase starting), then something serious is wrong, and you would need to contact ACTEL if they are who supplied the IP.

    JD
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