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A basic question about data bus transfer

Jerry Feng
Note: This was originally posted on 29th August 2011 at http://forums.arm.com

In AMBA AHB spec2.0 or AHB lite,
for the data bus transfer with byte, there is a table (Active byte lanes for a 32-bit little-endian data bus) as shown in the attachment.
I am kind of confused with it.
1.
For byte transmission, I thought it was fine by just putting the byte data on data[7:0], why do we need different lanes?

2.
For the address offset, where does it come from?
In another words, how can I know which lane is active?

I googled but could not find some answers, it seemed that everyone knew how to deal with it except me.

Can someone give me some advice on those questions?

Thank you very much.
  • Note: This was originally posted on 29th August 2011 at http://forums.arm.com

    Is the question too simple or other else?
    Can anyone tell me why I need to put byte in different lanes if I only need to transfer byte by byte?

    Thank you very much.
  • Note: This was originally posted on 3rd September 2011 at http://forums.arm.com

    Thank you very much.
    I got it.
    The low bits of HWADDR is used to identify offset.
    Then, if I want to transfer 8 bits in 32 bits bus in write mode, it will change its lane from time to time.

    However, I thought it is not a good idea to do this.
  • Arm Employee Badge
    Note: This was originally posted on 5th September 2011 at http://forums.arm.com


    However, I thought it is not a good idea to do this.


    Why not ?
  • Arm Employee Badge
    Note: This was originally posted on 30th August 2011 at http://forums.arm.com

    The AHB (or AHB-lite) HADDR bus states the address of the required transfer. If this transfer is a byte transfer the HADDR value will include the "address offset" that tells you which byte lane is being used. So tables 3-6 and 3-7 in the spec show you the active byte lane(s) for various width transfers for various LSB combinations of HADDR (the offsets).

    You cannot just attach an 8-bit device to D[7:0] only, it would need a MUX to select the relevant byte of the HWDATA bus, but for reads you could drive all bytes of the HRDATA bus with the same 8-bit read data value, and the AHB master will sample the byte from the correct byte lane it receives.

    JD