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Cortex-R4 : does "dual-issued pairs" really improve performance ?

Christophe Beausoleil
Note: This was originally posted on 1st August 2011 at http://forums.arm.com

Hello,

Could someone help me to explain that behavior :
I use a sequence of 4096 instructions (target is TMS570/Cortex-R4F) :
movs r0,#1
str r0, [r8~#0]
movs r1,#2
str r1, [r8~#4]
movs r2,#3
str r3, [r8~#8]
...

When "dual-issue" mode is enabled (bits 28-31 of Auxiliary Control  Register and bits 18-20 of Secondary Auxiliary Control Register are  reset), this code (plus a few instructions bordering it) executes in 5162 clock cycles.
When "dual-issue" mode is disabled (same bits are set), this code executes in 4146 clock cycles !!!

I observe this phenomenon for both ARM and Thumb2 modes.

So when "dual-issue" mode is enabled, it seems that one pipeline stage  is "sometimes" (once out of 4) waiting for dual words (thus introducing  extra wait states) in order to process them by pairs, but I can't find  any description of it.

Could someone help me to understand, please ? This is quite important for me,  because I have to produce highly deterministic real-time software, and  this kind of feature is hard to model...

Thanks for any help.

Best regards

Christophe
Parents
  • Arm Employee Badge
    Note: This was originally posted on 24th January 2012 at http://forums.arm.com

    Hello again. We've taken a quick look at this in a processor simulation and running your code does show the expected dual-issue benefit. We suspect that what you're seeing is due to the combination of rapid stores and instruction fetches somehow impacting the memory interface, flash pre-fetch etc. in the device you are using when dual-issue is working it hard. However, I'm sure you will see the benefit of dual issue on  a real piece of code. I hope this helps. Regards, Chris
Reply
  • Arm Employee Badge
    Note: This was originally posted on 24th January 2012 at http://forums.arm.com

    Hello again. We've taken a quick look at this in a processor simulation and running your code does show the expected dual-issue benefit. We suspect that what you're seeing is due to the combination of rapid stores and instruction fetches somehow impacting the memory interface, flash pre-fetch etc. in the device you are using when dual-issue is working it hard. However, I'm sure you will see the benefit of dual issue on  a real piece of code. I hope this helps. Regards, Chris
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