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Cortex-R4 : does "dual-issued pairs" really improve performance ?

Christophe Beausoleil
Note: This was originally posted on 1st August 2011 at http://forums.arm.com

Hello,

Could someone help me to explain that behavior :
I use a sequence of 4096 instructions (target is TMS570/Cortex-R4F) :
movs r0,#1
str r0, [r8~#0]
movs r1,#2
str r1, [r8~#4]
movs r2,#3
str r3, [r8~#8]
...

When "dual-issue" mode is enabled (bits 28-31 of Auxiliary Control  Register and bits 18-20 of Secondary Auxiliary Control Register are  reset), this code (plus a few instructions bordering it) executes in 5162 clock cycles.
When "dual-issue" mode is disabled (same bits are set), this code executes in 4146 clock cycles !!!

I observe this phenomenon for both ARM and Thumb2 modes.

So when "dual-issue" mode is enabled, it seems that one pipeline stage  is "sometimes" (once out of 4) waiting for dual words (thus introducing  extra wait states) in order to process them by pairs, but I can't find  any description of it.

Could someone help me to understand, please ? This is quite important for me,  because I have to produce highly deterministic real-time software, and  this kind of feature is hard to model...

Thanks for any help.

Best regards

Christophe
Parents
  • Arm Employee Badge
    Note: This was originally posted on 19th January 2012 at http://forums.arm.com

    Dual issue is described in a section at the end of the processor's Technical Reference Manual (TRM) which you can download from the support document resources on the ARM web site. You will see that only certain compbinations of instructions can dual issue and in fact there is not a completely duplicated pipeline within this processor (other ARM processors do have more extensive duplication of execution hardware).

    Hope this helps.


    Hello,

    Could someone help me to explain that behavior :
    I use a sequence of 4096 instructions (target is TMS570/Cortex-R4F) :
    movs r0,#1
    str r0, [r8~#0]
    movs r1,#2
    str r1, [r8~#4]
    movs r2,#3
    str r3, [r8~#8]
    ...

    When "dual-issue" mode is enabled (bits 28-31 of Auxiliary Control  Register and bits 18-20 of Secondary Auxiliary Control Register are  reset), this code (plus a few instructions bordering it) executes in 5162 clock cycles.
    When "dual-issue" mode is disabled (same bits are set), this code executes in 4146 clock cycles !!!

    I observe this phenomenon for both ARM and Thumb2 modes.

    So when "dual-issue" mode is enabled, it seems that one pipeline stage  is "sometimes" (once out of 4) waiting for dual words (thus introducing  extra wait states) in order to process them by pairs, but I can't find  any description of it.

    Could someone help me to understand, please ? This is quite important for me,  because I have to produce highly deterministic real-time software, and  this kind of feature is hard to model...

    Thanks for any help.

    Best regards

    Christophe
Reply
  • Arm Employee Badge
    Note: This was originally posted on 19th January 2012 at http://forums.arm.com

    Dual issue is described in a section at the end of the processor's Technical Reference Manual (TRM) which you can download from the support document resources on the ARM web site. You will see that only certain compbinations of instructions can dual issue and in fact there is not a completely duplicated pipeline within this processor (other ARM processors do have more extensive duplication of execution hardware).

    Hope this helps.


    Hello,

    Could someone help me to explain that behavior :
    I use a sequence of 4096 instructions (target is TMS570/Cortex-R4F) :
    movs r0,#1
    str r0, [r8~#0]
    movs r1,#2
    str r1, [r8~#4]
    movs r2,#3
    str r3, [r8~#8]
    ...

    When "dual-issue" mode is enabled (bits 28-31 of Auxiliary Control  Register and bits 18-20 of Secondary Auxiliary Control Register are  reset), this code (plus a few instructions bordering it) executes in 5162 clock cycles.
    When "dual-issue" mode is disabled (same bits are set), this code executes in 4146 clock cycles !!!

    I observe this phenomenon for both ARM and Thumb2 modes.

    So when "dual-issue" mode is enabled, it seems that one pipeline stage  is "sometimes" (once out of 4) waiting for dual words (thus introducing  extra wait states) in order to process them by pairs, but I can't find  any description of it.

    Could someone help me to understand, please ? This is quite important for me,  because I have to produce highly deterministic real-time software, and  this kind of feature is hard to model...

    Thanks for any help.

    Best regards

    Christophe
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