• Locked Locked
  • Replies 5 replies
  • Subscribers 118 subscribers
  • Views 3602 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Thumb mode, Thumb2 MRS insturction issue.

Kim DonaSam
Note: This was originally posted on 28th July 2011 at http://forums.arm.com

Dear All

I have find a strange behavior on cortexA9/R4,

My mode data code as below 

0x0   0x8100F3EF    MRS R1,CPSR                 (current CPSR value is 0x1F3)

However when I execute the line,  the value in R1 is 0x1D3,   Isn't it should be 0x1F3?

Is it a chip bug? or there is some other reason?

If anyone knows the answer, please let me know.
Parents
  • Note: This was originally posted on 1st August 2011 at http://forums.arm.com

    Hi,

    Answer is in DDI0406B (ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition), §B1.3.3 :
    The execution state bits are the IT[7:0], J, E, and T bits. In exception modes you can read or write these bits
    in the current SPSR.
    In the CPSR, unless the processor is in Debug state:
    "¢ The execution state bits, other than the E bit, are RAZ when read by an MRS instruction    .

    Regards

    Christophe
Reply
  • Note: This was originally posted on 1st August 2011 at http://forums.arm.com

    Hi,

    Answer is in DDI0406B (ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition), §B1.3.3 :
    The execution state bits are the IT[7:0], J, E, and T bits. In exception modes you can read or write these bits
    in the current SPSR.
    In the CPSR, unless the processor is in Debug state:
    "¢ The execution state bits, other than the E bit, are RAZ when read by an MRS instruction    .

    Regards

    Christophe
Children
No data