• Locked Locked
  • Replies 2 replies
  • Subscribers 117 subscribers
  • Views 4978 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex NVIC interrupt level and pulse type by software?

richard payne
Note: This was originally posted on 22nd July 2011 at http://forums.arm.com

I have read the ARM document about Cortex-M3 (or M0) and it say it can be used as level sensetive or pulse (edge) interrupt within the NVIC controller. The problem that it rather vague on how to do this, if this is done by software.

I fails to see any kind of register within the NVIC or such that control the type of the interrupt (to select edge or level by adjusting the register bits). So something must be done by software within handler but again it vague in this field.

It say I need to refer to chip vendor to establish if this is level or pulse type (for example LPC17xx), how they make it fixed, was is done by H/W outside Cortex module or configured by software to NVIC?

I like to hear anyone having a way to make it edge or level trigger interrupt by software if this is possible,. If so please demonstrate within the handler code (if this control it) that the make it detect for level or pulse.

If this is level detect, I can hold interrupt active which goes to handler and disable it, until restore by external code for which it re-execute the handler. This is what I'm trying to do as this is the way to check if the external signal remain in active state, but it will not work if this is pulse detect type.

I'm not talking about GPIO. .
  • Note: This was originally posted on 22nd July 2011 at http://forums.arm.com

    Thank, that is much clearer and make sense, it really edge and end of handler routine trigger rather than level after all!
  • Note: This was originally posted on 22nd July 2011 at http://forums.arm.com

    Hi there,

    There is no need to program the NVIC to handle level interrupt or pulse interrupt. It automatically handle both types.

    When there is a rising edge of the interrupt input, it set the pending status register, which cause the processor to service the interrupt if the interrupt is enabled. The pending status register is automatically cleared when the interrupt is seviced.  Even the interrupt input is still high during the execution of the interrupt handler, it won't set the pending status again. Unless if the interrupt input go low and then go high again (another rising edge), then the pending status will be set.

    When the interrupt handler exit, the pending status register samples the interrupt input again (automatically by hardware). So if the interrupt input is still high, it will set the pending status again and enter the interrupt handler again.

    If the interrupt is a pulse, it set the pending status register, which remain high until the interrupt is serviced. After the interrupt service is completed and exit, the interrupt source is inactive and return to the thread level.

    regards,
    Joseph