• Locked Locked
  • Replies 9 replies
  • Subscribers 119 subscribers
  • Views 8096 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Control MMU for TrustZone

thiet pv
Note: This was originally posted on 20th July 2011 at http://forums.arm.com

Dear all,
I am a new bie about TrustZone. I arm learning the effect of TrustZone to MMU. I have some problems about the mechanism to manage secure/non-secure region by MMU.
Please help me to understand about them.
My dubious point described as below:
   When translation virtual address to physical address, system will use TLB table. I know that, when have a miss occur on TLB, it will find physical page from page table.
From table index of virtual address and table base address, will have first-level descriptor, the first-level descriptor will be input for page table to get physical page table from page table
then fill it to TLB table.
If page table miss, it will find physical page form external memory (RAM) and fill it to page table with it's attribute.
So when cpu stay in secure world, and access to secure physical memory
     How to know the address that cpu access include secure physical memory region or no-secure physical memory region?
     How to partition the physical memory into secure and non-secure regions?
and if know secure attribute of secure region then
     How to fill secure attribute to page table?
Please help me.
Thank you very much,
Parents
  • Arm Employee Badge
    Note: This was originally posted on 21st July 2011 at http://forums.arm.com

    There are two things to bare in mind:

    • Which world the TLB entry belongs to
    • Whether the memory being described should be accessed using secure or non-secure accesses
    The first one is automatic.  If the TLB entry is pulled in while in the Secure world, it will be marked as a "Secure" TLB entry.  ONLY THE SECURE WORLD WILL BE ABLE TO USE THIS ENTRY.  If the TLB entry is pulled in while in the Normal world, it will be marked as a "Non-Secure" TLB entry.  ONLY THE NORMAL WORLD WILL BE ABLE TO USE THIS ENTRY.

    The second one then...  The Normal world can only generate non-secure memory accesses.  So when a Normal world TLB entry is used, the processor will just assume that any accesses with be marked non-secure.

    The SEcure world can generate secure or non-secure accesses.  What will be used for given address range is controlled by the NS bit in the descriptors.  For Secure world TLB entries, the value of this bit is stored along side teh translation and other attributes.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 21st July 2011 at http://forums.arm.com

    There are two things to bare in mind:

    • Which world the TLB entry belongs to
    • Whether the memory being described should be accessed using secure or non-secure accesses
    The first one is automatic.  If the TLB entry is pulled in while in the Secure world, it will be marked as a "Secure" TLB entry.  ONLY THE SECURE WORLD WILL BE ABLE TO USE THIS ENTRY.  If the TLB entry is pulled in while in the Normal world, it will be marked as a "Non-Secure" TLB entry.  ONLY THE NORMAL WORLD WILL BE ABLE TO USE THIS ENTRY.

    The second one then...  The Normal world can only generate non-secure memory accesses.  So when a Normal world TLB entry is used, the processor will just assume that any accesses with be marked non-secure.

    The SEcure world can generate secure or non-secure accesses.  What will be used for given address range is controlled by the NS bit in the descriptors.  For Secure world TLB entries, the value of this bit is stored along side teh translation and other attributes.
Children
No data