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Control MMU for TrustZone

thiet pv
Note: This was originally posted on 20th July 2011 at http://forums.arm.com

Dear all,
I am a new bie about TrustZone. I arm learning the effect of TrustZone to MMU. I have some problems about the mechanism to manage secure/non-secure region by MMU.
Please help me to understand about them.
My dubious point described as below:
   When translation virtual address to physical address, system will use TLB table. I know that, when have a miss occur on TLB, it will find physical page from page table.
From table index of virtual address and table base address, will have first-level descriptor, the first-level descriptor will be input for page table to get physical page table from page table
then fill it to TLB table.
If page table miss, it will find physical page form external memory (RAM) and fill it to page table with it's attribute.
So when cpu stay in secure world, and access to secure physical memory
     How to know the address that cpu access include secure physical memory region or no-secure physical memory region?
     How to partition the physical memory into secure and non-secure regions?
and if know secure attribute of secure region then
     How to fill secure attribute to page table?
Please help me.
Thank you very much,
Parents
  • Arm Employee Badge
    Note: This was originally posted on 20th July 2011 at http://forums.arm.com

    The L1 page table entries contain an "NS" bit which defines whether the memory is secure (NS=0) or non-secure (NS=1). This security setting applies to sections, or to all pages in an L2 table.

    The NS bit is ignored if the processor is running in the "non-secure" world, the hardware forces NS=1 in this case.

    Iso
Reply
  • Arm Employee Badge
    Note: This was originally posted on 20th July 2011 at http://forums.arm.com

    The L1 page table entries contain an "NS" bit which defines whether the memory is secure (NS=0) or non-secure (NS=1). This security setting applies to sections, or to all pages in an L2 table.

    The NS bit is ignored if the processor is running in the "non-secure" world, the hardware forces NS=1 in this case.

    Iso
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