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Cortex-A9 L2 Cache simulation

Note: This was originally posted on 28th June 2011 at http://forums.arm.com

Hi,

I'm trying to do some development for the Cortex-A9. I'm using RealView and have been able to get the real-time system model working.

I want to play around with the cache controller a bit, specifically cache locking, but I haven't been able to get the cache behaviour to model. I based my project off the Cortex-A9 Cached Dhrystone example, so I have the code from that to do cache and mmu init. I also downloaded the Cortex-A9MP PL310 Dhrystone example and built and ran that, which at the end states "L2 Data Read Hits = 0", which seems unlikely.

Is the cache simulated in the RealView Debugger? I turned on memory colouring to show L1 and L2 clean/dirty stuff, but none of the colours show up (just the blue and light blue to indicate changes). If the debugger does not provide this, how can I go about testing this? Is there another simulator/emulator that has cache support? Can I plug real hardware into the debugger and use that?

Thanks,
Patrick

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Tom Jacobs over 12 years ago

Note: This was originally posted on 29th June 2011 at http://forums.arm.com

Patrick,

The models in RVDS do not model the functionality of the caches, just register view. The models in the Fast Models product can model the functionality of the caches however. You can download an 45day eval of the Fast Models from here:

https://silver.arm.com/

RVD can still be used to debug the Fast Models

Tom
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Tom Jacobs over 12 years ago

Note: This was originally posted on 29th June 2011 at http://forums.arm.com

Patrick,

The models in RVDS do not model the functionality of the caches, just register view. The models in the Fast Models product can model the functionality of the caches however. You can download an 45day eval of the Fast Models from here:

https://silver.arm.com/

RVD can still be used to debug the Fast Models

Tom
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