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Cortex-A9 L2 Cache simulation

Patrick Colp
Note: This was originally posted on 28th June 2011 at http://forums.arm.com

Hi,

I'm trying to do some development for the Cortex-A9. I'm using RealView and have been able to get the real-time system model working.

I want to play around with the cache controller a bit, specifically cache locking, but I haven't been able to get the cache behaviour to model. I based my project off the Cortex-A9 Cached Dhrystone example, so I have the code from that to do cache and mmu init. I also downloaded the Cortex-A9MP PL310 Dhrystone example and built and ran that, which at the end states "L2 Data Read Hits = 0", which seems unlikely.

Is the cache simulated in the RealView Debugger? I turned on memory colouring to show L1 and L2 clean/dirty stuff, but none of the colours show up (just the blue and light blue to indicate changes). If the debugger does not provide this, how can I go about testing this? Is there another simulator/emulator that has cache support? Can I plug real hardware into the debugger and use that?

Thanks,
Patrick
Parents
  • Note: This was originally posted on 1st July 2011 at http://forums.arm.com

    I found the answers to my questions in some of the documentation that came with Fast Model (DUI0423J_fast_model_rm.pdf).

    Basically:


    The following features of the PL310 hardware are not implemented in the PL310 model, most
    of them are not relevant from a PV modelling point of view:
      "¢ There is no interface to the data and tag RAM as they are embedded to the model.

      "¢ L2 cache event monitoring is not supported.
      "¢ Performance counters are not supported.

    So while I can model the behaviour (affect on load time of data) and I can (in theory) lock cache lines, the only way I'll know if it's working is if the cycle count is less -- and this won't help be determine details of the locking behaviour.

    Thanks for all your help Tom. Maybe I can hack the model to make it do what I want...
Reply
  • Note: This was originally posted on 1st July 2011 at http://forums.arm.com

    I found the answers to my questions in some of the documentation that came with Fast Model (DUI0423J_fast_model_rm.pdf).

    Basically:


    The following features of the PL310 hardware are not implemented in the PL310 model, most
    of them are not relevant from a PV modelling point of view:
      "¢ There is no interface to the data and tag RAM as they are embedded to the model.

      "¢ L2 cache event monitoring is not supported.
      "¢ Performance counters are not supported.

    So while I can model the behaviour (affect on load time of data) and I can (in theory) lock cache lines, the only way I'll know if it's working is if the cycle count is less -- and this won't help be determine details of the locking behaviour.

    Thanks for all your help Tom. Maybe I can hack the model to make it do what I want...
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