• Locked Locked
  • Replies 6 replies
  • Subscribers 119 subscribers
  • Views 5012 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-A9 L2 Cache simulation

Patrick Colp
Note: This was originally posted on 28th June 2011 at http://forums.arm.com

Hi,

I'm trying to do some development for the Cortex-A9. I'm using RealView and have been able to get the real-time system model working.

I want to play around with the cache controller a bit, specifically cache locking, but I haven't been able to get the cache behaviour to model. I based my project off the Cortex-A9 Cached Dhrystone example, so I have the code from that to do cache and mmu init. I also downloaded the Cortex-A9MP PL310 Dhrystone example and built and ran that, which at the end states "L2 Data Read Hits = 0", which seems unlikely.

Is the cache simulated in the RealView Debugger? I turned on memory colouring to show L1 and L2 clean/dirty stuff, but none of the colours show up (just the blue and light blue to indicate changes). If the debugger does not provide this, how can I go about testing this? Is there another simulator/emulator that has cache support? Can I plug real hardware into the debugger and use that?

Thanks,
Patrick
Parents
  • Note: This was originally posted on 1st July 2011 at http://forums.arm.com

    Playing around with things a bit more, if I use the Model Debugger that comes with Fast Models then I can at least add PL310 to the model and have it open a window showing the cache lines. I can also see the cache registers. It looks like I can affect the registers (like toggling the L2 enabled bit), but the data lines all stay empty.

    Do I have to do something like add an L1 cache as well?
Reply
  • Note: This was originally posted on 1st July 2011 at http://forums.arm.com

    Playing around with things a bit more, if I use the Model Debugger that comes with Fast Models then I can at least add PL310 to the model and have it open a window showing the cache lines. I can also see the cache registers. It looks like I can affect the registers (like toggling the L2 enabled bit), but the data lines all stay empty.

    Do I have to do something like add an L1 cache as well?
Children
No data