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AXI 3/AXI 4 Exclusive Access

Note: This was originally posted on 14th June 2011 at http://forums.arm.com

Hi,

I have a query  regarding Exclusive Access in AXI 3/ AXI 4. The spec does NOT say anything about this behavior, hence I need a clarification.

1. Can there be two Exclusive Reads monitoring the same address region?

   ARID = 0    ARADDR = 0x004   ARSIZE = 0   ARLEN = 2
   ARID = 3    ARADDR = 0x004   ARSIZE = 1   ARLEN = 1

** Lets assume the above ID's have come sequentially in subsequent cycles and NO exclusive write has come.

2. If YES, then How should the behavior of Exclusive Write be?
a. Exclusive Write of which ID should be entertained?
        b. Should we stop monitoring the OTHER ID when the exclusive write for ONE ID arrives?

3. In case of a successful Exclusive Write, is there a compulsion for the slave to send EXOKAY?
    a. Can it also send SLVERR, or DECERR?

Regards,
Sai Karthik
Parents
  • Note: This was originally posted on 14th June 2011 at http://forums.arm.com


    I have a query  regarding Exclusive Access in AXI 3/ AXI 4. The spec does NOT say anything about this behavior, hence I need a clarification.

    AXI is only the carrier of the respective signals. Exclusive access is defined in the ARM ARM.


    1. Can there be two Exclusive Reads monitoring the same address region?

       ARID = 0    ARADDR = 0x004   ARSIZE = 0   ARLEN = 2
       ARID = 3    ARADDR = 0x004   ARSIZE = 1   ARLEN = 1

    Yes.

    2. If YES, then How should the behavior of Exclusive Write be?
    a. Exclusive Write of which ID should be entertained?
            b. Should we stop monitoring the OTHER ID when the exclusive write for ONE ID arrives?

    a. Either. Exclusive write is based on a first come first served strategy. The whole idea of exclusive access was to prevent bus contention caused by one master holding on to resources for a generous amount of time. If a specific order were required, perhaps even deadlocks could occur.
    b. Yes. All monitors of the same address (range) will have to be cleared.

    3. In case of a successful Exclusive Write, is there a compulsion for the slave to send EXOKAY?
        a. Can it also send SLVERR, or DECERR?

    This question is strange. Why would it want to return anything but EXOKAY for a successful exclusive write?

    Kindly,
    Marcus
Reply
  • Note: This was originally posted on 14th June 2011 at http://forums.arm.com


    I have a query  regarding Exclusive Access in AXI 3/ AXI 4. The spec does NOT say anything about this behavior, hence I need a clarification.

    AXI is only the carrier of the respective signals. Exclusive access is defined in the ARM ARM.


    1. Can there be two Exclusive Reads monitoring the same address region?

       ARID = 0    ARADDR = 0x004   ARSIZE = 0   ARLEN = 2
       ARID = 3    ARADDR = 0x004   ARSIZE = 1   ARLEN = 1

    Yes.

    2. If YES, then How should the behavior of Exclusive Write be?
    a. Exclusive Write of which ID should be entertained?
            b. Should we stop monitoring the OTHER ID when the exclusive write for ONE ID arrives?

    a. Either. Exclusive write is based on a first come first served strategy. The whole idea of exclusive access was to prevent bus contention caused by one master holding on to resources for a generous amount of time. If a specific order were required, perhaps even deadlocks could occur.
    b. Yes. All monitors of the same address (range) will have to be cleared.

    3. In case of a successful Exclusive Write, is there a compulsion for the slave to send EXOKAY?
        a. Can it also send SLVERR, or DECERR?

    This question is strange. Why would it want to return anything but EXOKAY for a successful exclusive write?

    Kindly,
    Marcus
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