We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
The reason to have half of the RAM in CODE region is to have high speed program execution from SRAM. By having two SRAM units, you can have data and instruction accesses at the same time (havard bus architecture).To use this, you need to copy your program code (or at least some part of it) from flash to this SRAM in CODE region, usually during start up process. (Note: You need to link your program correctly to match the run time memory map).Although NXP has a flash memory prefetch unt, which avoid wait state in sequential accesses, wait state of the flash memory still affect the performance in branches, or some other non-sequential accesses to flash. By using this SRAM for program execution, you can eliminate the effect of flash wait state.From my understanding there is nothing to stop you from using this SRAM (in CODE region) for stack or data variables. But this SRAM region is not covered by bit-band feature. And depending on how NXP implement the bus interconnections, you might (Note: I don't know, you need to do your own benchmark) find that performance of the system reduced because stack/data operations and program accesses use the same bus (it became von Neumann bus architecture).regards,Joseph