• Locked Locked
  • Replies 8 replies
  • Subscribers 119 subscribers
  • Views 10913 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-M3 Memory management fault recovery

sam sun
Note: This was originally posted on 2nd June 2011 at http://forums.arm.com

Hi, is the Cortex-M3 supposed the user to do mannual instructions to recovery from the memory management fault handler?

After enable the MPU feature on my Cortex-M3 processor and stepped into the illegal access instruction, the MMF exception would generated as expected. But after executing of the normal MMF exception handler, the program would go back to the illegal access instruction again! We have inspected the stack of entering the MMF exception, the PC pushed is exactly the illegal instruction, that would be the cause of the loop. So is this the definition of the Cortex-M3 familiy?

The other exceptions would normally adjust the PC value to the next instruction before entering the exception, liked system tick or other IRQs.

BR
Parents
  • Note: This was originally posted on 8th June 2011 at http://forums.arm.com

    Hi, Joseph,

    Thanks for the very helpful information. Sorry for this late feedback as i just returned from a holiday.

    From your answer, do you mean the Cortex-M3 is always defined the MMF exception the behavior as your described above? Or it could be designed to return to the next instruction? I mean the Cortex-M3 is always defined as your answer exactly.

    Once we have used another individual MPU IP core with ARM7, it is returned to the next instruction. This really puzzled us.

    B.R.
    Sam
Reply
  • Note: This was originally posted on 8th June 2011 at http://forums.arm.com

    Hi, Joseph,

    Thanks for the very helpful information. Sorry for this late feedback as i just returned from a holiday.

    From your answer, do you mean the Cortex-M3 is always defined the MMF exception the behavior as your described above? Or it could be designed to return to the next instruction? I mean the Cortex-M3 is always defined as your answer exactly.

    Once we have used another individual MPU IP core with ARM7, it is returned to the next instruction. This really puzzled us.

    B.R.
    Sam
Children
No data