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ArmCC Code optimisation

Jude Baby
Note: This was originally posted on 1st June 2011 at http://forums.arm.com

Hi,

I am trying to generate an assembly code for the following C structure access using armcc

typedef struct
{
  char a : 4 ;
  char b : 4 ;
} struct1 ;

Variables a and b are 4bits each

I have the following function

void fun1 (struct * ip)
{
  ip->a = 1 ;
  ip->b = 2 ;
}

The assembly instructions generated for the following code with optimization O2 is as follows
The ARM Compiler / assembler version is 4.1 [build 514]

;;;31  void fun1(struct1 * ip)
;;;31  {
;;;31    ip->a = 1;
     0x01004688: e5d01000 .... LDRB  r1,[r0,#0]
     0x0100468c: e3c1100f .... BIC   r1,r1,#0xf
     0x01004690: e2811001 .... ADD   r1,r1,#1
;;;32    ip->b = 2;
     0x01004694: e3c110f0 .... BIC   r1,r1,#0xf0
     0x01004698: e2811020  ... ADD   r1,r1,#0x20
     0x0100469c: e5c01000 .... STRB  r1,[r0,#0]
;;;33  }

Here fields [3:0] and [7:4] of the register r1 are updated using
4 instructions , 2 BIC and 2 ADD .

Is a compiler optimization possible to further reduce the number of instructions ?
I was hoping that it would further be reduced to 2 instructions as

BIC   r1 , r1 , #0xff
ADD r1 , r1 , #0x21

or somthing like

MOV  r1 , #21



Regards
Jude