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PMU in Cortex-A8 (OMAP 3530) - What am I doing wrong?

Ted Middleton
Note: This was originally posted on 1st June 2011 at http://forums.arm.com

I've been trying to use the PMU in the OMAP3530 (on a beagleboard) to do some profiling, but I don't seem to be able to get the 4 PMU counters to do anything - they always read 0. The cycle counter works well enough. Here's some disassembly from the code that I'm running:



...

;;    _setCounting(1)
ee19 1f1c    mrc  15, 0, r1, cr9, cr12, {0}
f041 0001    orr.w   r0, r1, #1
ee09 0f1c    mcr  15, 0, r0, cr9, cr12, {0}

;;    _resetClockCounter();
ee19 3f1c    mrc  15, 0, r3, cr9, cr12, {0}
f043 0704    orr.w   r7, r3, #4
ee09 7f1c    mcr  15, 0, r7, cr9, cr12, {0}

;;    _resetEventCounters();
ee19 6f1c    mrc  15, 0, r6, cr9, cr12, {0}
f046 0c02    orr.w   ip, r6, #2
ee09 cf1c    mcr  15, 0, ip, cr9, cr12, {0}

;;    _selectPerfCounter(0);
;;    _setPerfCounterFunction( count0func=0x8 );
2200            movs    r2, #0
ee09 2fbc    mcr  15, 0, r2, cr9, cr12, {5}
2108            movs    r1, #8
ee09 1f3d    mcr  15, 0, r1, cr9, cr13, {1}

;;    _selectPerfCounter(1);
;;    _setPerfCounterFunction( count1func=0xf );
2001            movs    r0, #1
ee09 0fbc    mcr  15, 0, r0, cr9, cr12, {5}
230f            movs    r3, #15
ee09 3f3d    mcr  15, 0, r3, cr9, cr13, {1}

;;    _selectPerfCounter(2);
;;    _setPerfCounterFunction( count2func=0x11 );
2702            movs    r7, #2
ee09 7fbc    mcr  15, 0, r7, cr9, cr12, {5}
2611            movs    r6, #17
ee09 6f3d    mcr  15, 0, r6, cr9, cr13, {1}

;;    _selectPerfCounter(3);
;;    _setPerfCounterFunction( count3func=0x40 );
2203            movs    r2, #3
ee09 2fbc    mcr  15, 0, r2, cr9, cr12, {5}
2140            movs    r1, #64 ; 0x40
ee09 1f3d    mcr  15, 0, r1, cr9, cr13, {1}

;;    _enableCounters(1, 1, 1, 1, 1);
200f            movs    r0, #15
f2c8 0000    movt    r0, #32768      ; 0x8000
ee09 0f3c    mcr  15, 0, r0, cr9, cr12, {1}

...


After this, when I read from the PMU registers, this is what I see:


PMNC:   41002001 
CNTENS: 8000000f       
CNTENC: 8000000f  
FLAG:   00000000  
CCNT:   0000009f 
PMCNT0: 00000000       
PMCNT1: 00000000       
PMCNT2: 00000000       
PMCNT3: 00000000       
USEREN: 00000001


Any ideas what I'm doing wrong here?
Parents
  • Note: This was originally posted on 7th June 2011 at http://forums.arm.com


    You have to enable performance monitoring while in supervisor mode. If you're running Linux that means loading up a kernel module to do it. This should help you:

    http://stackoverflow...ex-a8-processor


    I've had a look at that, and it doesn't seem to apply...unless there's something else that I don't know. In particular, the USEREN bit is already set for me (as you can see from the register output I've posted). This was the proposed solution in the stackoverflow answer, but it seems that this has already been done for me.

    I've tried the above code in kernel mode (in my boot loader before the OS loads) and it works just fine. I get a cycle counter AND the performance counters. Once I'm in user mode though, only the cycle counter works. The ARMv7 and Cortex-A8 docs both say that the USEREN reg controls access to ALL of the PMU registers. IOW I wouldn't be getting the cycle counter at all if the USEREN wasn't set to allow user mode access.

    Is there any other security or access system that might be resetting my performance counters while allowing access to the cycle counter? Does anyone know enough about Angstrom and oprofile to know whether they could somehow be interfering with my access to the performance counters (although I can't imagine how they would be doing this)?. Should I be asking the oprofile and Angstrom people about this?
Reply
  • Note: This was originally posted on 7th June 2011 at http://forums.arm.com


    You have to enable performance monitoring while in supervisor mode. If you're running Linux that means loading up a kernel module to do it. This should help you:

    http://stackoverflow...ex-a8-processor


    I've had a look at that, and it doesn't seem to apply...unless there's something else that I don't know. In particular, the USEREN bit is already set for me (as you can see from the register output I've posted). This was the proposed solution in the stackoverflow answer, but it seems that this has already been done for me.

    I've tried the above code in kernel mode (in my boot loader before the OS loads) and it works just fine. I get a cycle counter AND the performance counters. Once I'm in user mode though, only the cycle counter works. The ARMv7 and Cortex-A8 docs both say that the USEREN reg controls access to ALL of the PMU registers. IOW I wouldn't be getting the cycle counter at all if the USEREN wasn't set to allow user mode access.

    Is there any other security or access system that might be resetting my performance counters while allowing access to the cycle counter? Does anyone know enough about Angstrom and oprofile to know whether they could somehow be interfering with my access to the performance counters (although I can't imagine how they would be doing this)?. Should I be asking the oprofile and Angstrom people about this?
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