• Locked Locked
  • Replies 5 replies
  • Subscribers 118 subscribers
  • Views 4589 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

secure & non-secure address space in Cotex-A9

jianhui li
Note: This was originally posted on 11th May 2011 at http://forums.arm.com

Dear professor,
I would like to know how is it implemented the separate address space between secure state and non-secure state in Cotex-A9?
" When implemented, the Security Extensions provide two physical address spaces, a Secure physical address space and a Non-secure physical address space."
this is described in the datasheet of ARMv7.
And I understand that secure and non-secure state has separete translation table according to different TTB registers copy.
but i am confused how do they have separe physical address space?

Parents
  • Note: This was originally posted on 11th May 2011 at http://forums.arm.com

    thanks so much for your explanation.
    But I am still not very clear about the following question.
    if the whole address space is 0 ~ 100, and I want assign 0 ~ 100 to the secure space and 21 ~ 100 to the non-secure space.
    how to do this? is this done by HW or SW?
    thanks so much!
Reply
  • Note: This was originally posted on 11th May 2011 at http://forums.arm.com

    thanks so much for your explanation.
    But I am still not very clear about the following question.
    if the whole address space is 0 ~ 100, and I want assign 0 ~ 100 to the secure space and 21 ~ 100 to the non-secure space.
    how to do this? is this done by HW or SW?
    thanks so much!
Children
No data