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Alignment in Cortex-M3 and RVDS

Sagar Jadhav
Note: This was originally posted on 6th May 2011 at http://forums.arm.com

Hi all,

I am using RVDS 4.1 for debugging a Corex-M3 based target. I am facing an alignment issue. My code is making 2-byte as well as 4-byte aligned access. I want it to make only 4-byte aligned access.

1. Can anyone tell me how I can find out whether program is making or not a 4-byte aligned access(of instruction or data)?
2. Can i know whether a function (in disassembly) or a section in scatter loading file is 4-byte aligned or not??
3. Can you suggest anything i can make use of in my scatter loading file (I am using 'ALIGNALL 4' option for a few regions, but randomly)??

4. Also, which instruction set does Cortex-M3 use - ARM or THUMB or THUMB-2 or any combination of these 3?

Thanks,
Sagar.
Parents
  • Arm Employee Badge
    Note: This was originally posted on 13th May 2011 at http://forums.arm.com

    1. For instructions in Cortex-M3, it can be 2 bytes in size or 4 bytes in size. Therefore the instructions can be in 4 bytes or 2 bytes aligned locations. The actual instruction fetches are always 4 bytes in size and aligned to 4 byte address boundaries.

    Data in ARM can be byte, halfword (2 bytes), word (4 bytes) or even double word ( 8 bytes). Cortex-M3 can generate accesses based on the data size (except for double word data, which is handled with multiple accesses on the bus).
    Normally data transfers are aligned to size, unless you directly setting up pointers in C to create unaligned data, or use pack structures.

    The Cortex-M3 can be setup to detect unaligned transfer by setting UNALIGN_TRP (bit 3) of Configuration Control Register (@0xE000ED14). However, this is a bit different from your question of "find out whether program is making or not a 4-byte aligned access(of instruction or data)".

    4. Cortex-M3 is Thumb only, and support both 16-bit and 32-bit Thumb instructions. The supports of this mixing of 16-bit and 32-bit instructions is called Thumb-2 Technology.

    I don't have answer for question 2 and 3 at the moment.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 13th May 2011 at http://forums.arm.com

    1. For instructions in Cortex-M3, it can be 2 bytes in size or 4 bytes in size. Therefore the instructions can be in 4 bytes or 2 bytes aligned locations. The actual instruction fetches are always 4 bytes in size and aligned to 4 byte address boundaries.

    Data in ARM can be byte, halfword (2 bytes), word (4 bytes) or even double word ( 8 bytes). Cortex-M3 can generate accesses based on the data size (except for double word data, which is handled with multiple accesses on the bus).
    Normally data transfers are aligned to size, unless you directly setting up pointers in C to create unaligned data, or use pack structures.

    The Cortex-M3 can be setup to detect unaligned transfer by setting UNALIGN_TRP (bit 3) of Configuration Control Register (@0xE000ED14). However, this is a bit different from your question of "find out whether program is making or not a 4-byte aligned access(of instruction or data)".

    4. Cortex-M3 is Thumb only, and support both 16-bit and 32-bit Thumb instructions. The supports of this mixing of 16-bit and 32-bit instructions is called Thumb-2 Technology.

    I don't have answer for question 2 and 3 at the moment.
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