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ARM Cache Issues

Mike Hooper
Note: This was originally posted on 29th April 2011 at http://forums.arm.com

Hello fellow ARMers! I am new to the forum, and new to ARM programming.....so go easy on me...:)

I am trying to improve the performance of my algorithm on the ARM side of a TI OMAP-L138 chip. The ARM processor is the ARM926EJ-S™. Is this the correct place to post?

My issue is, when I attempt to enable I and D caches the program crashes. The crash is very ugly (totally corrupted memory) if I enable MMU, but less ugly (program simply restarts itself at main.c) if I disable MMU. Here is my code, which I call just after enabling privileged mode.



CP15_CTL_MMU_ENABLE   .equ 0x0001
CP15_CTL_ALIGN_FAULT_ENABLE .equ 0x0002
CP15_CTL_INST_CACHE_ENABLE .equ 0x0004
CP15_CTL_DATA_CACHE_ENABLE .equ 0x1000

;__CACHE_enable .long CACHE_enable

.global CACHE_enable

CACHE_enable:.asmfunc
mov r0, #0
mrc p15, #0, r0, c1, c0, #0
; orr r0, r0, #CP15_CTL_MMU_ENABLE
orr r0, r0, #CP15_CTL_ALIGN_FAULT_ENABLE
orr r0, r0, #CP15_CTL_INST_CACHE_ENABLE
orr r0, r0, #CP15_CTL_DATA_CACHE_ENABLE
mcr p15, #0, r0, c1, c0, #0
mov r0, r0
mov r0, r0
mov r0, r0
mov r0, r0
mov r0, r0
.endasmfunc




I basically copied this code from another post over on the TI E2E forum. Can someone give some guidance on what may be going wrong? I appreciate your help!

Thx,
MikeH
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