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Secondary CPU Boot-Up

Sajid Rabbani Avagundam
Note: This was originally posted on 21st April 2011 at http://forums.arm.com

Environment: ARM-CA9 MultiCore

Pre-condition: Boot monitor starts all the cores together and later continues with primary CPU0, where as the secondary CPU1, CPU2, ... are moved to wait for interrupt condition with WFI instruction.

-------------------- snippet start (secondary CPU wait state)
loop:
wfi
ldr  pc, loop
-------------------- snippet end


Question: For primary CPU, later when boot monitor gives control to u-boot software and finally u-boot gives control to application software. In this application context, if the primary CPU wants to wakeup the secondary CPUs, it basically needs to interrupt them, below observations was done:
  • no interrupt handling was observed by secondary CPUs
  • but when, above shown snippet was modifed to include a 'nop' instruction after WFI instruction, the secondary CPUs started handling interrupts
I assume that this is because of the way the return from interrupt handling is done, something like LR+4, LR, ... so on.

Please clarify/reason-out why it is working in the later modified condition? Or what is the actual procedure to wake up secondary CPUs using interrupts ...
Parents
  • Arm Employee Badge
    Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    As you're looking at the disassembly, how are you inserting the NOP?

    How are you checking whether the interrupt is taken?  By breakpointing the IRQ vector, or just by seeing whether any appears to happen?

    What does the IRQ handler do?  Does it return with the standard sequence (SUBS pc, lr, #4 or equivalent), or to some other address?
Reply
  • Arm Employee Badge
    Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    As you're looking at the disassembly, how are you inserting the NOP?

    How are you checking whether the interrupt is taken?  By breakpointing the IRQ vector, or just by seeing whether any appears to happen?

    What does the IRQ handler do?  Does it return with the standard sequence (SUBS pc, lr, #4 or equivalent), or to some other address?
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