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Secondary CPU Boot-Up

Sajid Rabbani Avagundam
Note: This was originally posted on 21st April 2011 at http://forums.arm.com

Environment: ARM-CA9 MultiCore

Pre-condition: Boot monitor starts all the cores together and later continues with primary CPU0, where as the secondary CPU1, CPU2, ... are moved to wait for interrupt condition with WFI instruction.

-------------------- snippet start (secondary CPU wait state)
loop:
wfi
ldr  pc, loop
-------------------- snippet end


Question: For primary CPU, later when boot monitor gives control to u-boot software and finally u-boot gives control to application software. In this application context, if the primary CPU wants to wakeup the secondary CPUs, it basically needs to interrupt them, below observations was done:
  • no interrupt handling was observed by secondary CPUs
  • but when, above shown snippet was modifed to include a 'nop' instruction after WFI instruction, the secondary CPUs started handling interrupts
I assume that this is because of the way the return from interrupt handling is done, something like LR+4, LR, ... so on.

Please clarify/reason-out why it is working in the later modified condition? Or what is the actual procedure to wake up secondary CPUs using interrupts ...
Parents
  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com


    Couple of  questions, do you have the CPSR.I bit clear and how do you send the interrupt?


    Boot monitor source code is not-available at present. i have analyzed the assembly source code (disassembly) when we dump the vector area and its vicinity. However, i infer that CPSR.I is definitely cleared, because just by introducing the 'nop' instruction the interrupt is generated and handled.

    Interrupt from primary CPU to secondary CPUs is done using Software Generated Interrupt Register (ICDSGIR).
Reply
  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com


    Couple of  questions, do you have the CPSR.I bit clear and how do you send the interrupt?


    Boot monitor source code is not-available at present. i have analyzed the assembly source code (disassembly) when we dump the vector area and its vicinity. However, i infer that CPSR.I is definitely cleared, because just by introducing the 'nop' instruction the interrupt is generated and handled.

    Interrupt from primary CPU to secondary CPUs is done using Software Generated Interrupt Register (ICDSGIR).
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