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Flags of APSR Register in Cortex M3

Muhammad Ahsan
Note: This was originally posted on 19th April 2011 at http://forums.arm.com

Hello all,
I am having probelm in writing Flags of APSR Register in Cortex M3. The result of a comparison cuases the negative flag to get set to 1. Next instruction reads the APSR using MRS instruction. Before executing this instruction I clear the negative flag to 0. If I execute the instruction of reading the APSR after clearing the negative flag, program jumps to hardfault handler. Reference manual states that these flags are writable.
We can write APSR using MSR instruction too. But is it possible to change a single bit(Flag) as I have mentioned above?
Thanks in advance
Parents
  • Arm Employee Badge
    Note: This was originally posted on 22nd April 2011 at http://forums.arm.com

    Hi,

    I have tested this using Keil MDK with ULINK2 with Cortex-M3 r2p0 but didn't get any problem.
    I used a simple test
    __asm void test_1(void)
    {
       MOVS  R0, #0     ; Breakpoint set here, then single step through
       MOVS  R1, #
       SUBS  R0, R0, R1  ; Set N flag, then use MDK uVision debug to clear N bit to 0
       MRS   R0, APSR
       BX   LR
    }
    It might worth checking the value of xPSR before and after the change to see if the debugger change other bits.
    Also, when it enter hard fault, please check the values of various fault staus registers.

    It might also worth email IAR to see if they are aware of any known problem which might affect this.

    I am away next week so won't be able to check the forum until May.

    regards,
    Joseph
Reply
  • Arm Employee Badge
    Note: This was originally posted on 22nd April 2011 at http://forums.arm.com

    Hi,

    I have tested this using Keil MDK with ULINK2 with Cortex-M3 r2p0 but didn't get any problem.
    I used a simple test
    __asm void test_1(void)
    {
       MOVS  R0, #0     ; Breakpoint set here, then single step through
       MOVS  R1, #
       SUBS  R0, R0, R1  ; Set N flag, then use MDK uVision debug to clear N bit to 0
       MRS   R0, APSR
       BX   LR
    }
    It might worth checking the value of xPSR before and after the change to see if the debugger change other bits.
    Also, when it enter hard fault, please check the values of various fault staus registers.

    It might also worth email IAR to see if they are aware of any known problem which might affect this.

    I am away next week so won't be able to check the forum until May.

    regards,
    Joseph
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