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Flags of APSR Register in Cortex M3

Muhammad Ahsan
Note: This was originally posted on 19th April 2011 at http://forums.arm.com

Hello all,
I am having probelm in writing Flags of APSR Register in Cortex M3. The result of a comparison cuases the negative flag to get set to 1. Next instruction reads the APSR using MRS instruction. Before executing this instruction I clear the negative flag to 0. If I execute the instruction of reading the APSR after clearing the negative flag, program jumps to hardfault handler. Reference manual states that these flags are writable.
We can write APSR using MSR instruction too. But is it possible to change a single bit(Flag) as I have mentioned above?
Thanks in advance
Parents
  • Arm Employee Badge
    Note: This was originally posted on 20th April 2011 at http://forums.arm.com

    How do you clear the APSR? By a debugger?

    If you write 0 to the xPSR using a debugger (only a guess), you might have accidentally cleared the T bit (Thumb state). This cause a fault exception when you step into the next instruction as it means you are trying to execute an ARM instruction.

    regards,
    Joseph
Reply
  • Arm Employee Badge
    Note: This was originally posted on 20th April 2011 at http://forums.arm.com

    How do you clear the APSR? By a debugger?

    If you write 0 to the xPSR using a debugger (only a guess), you might have accidentally cleared the T bit (Thumb state). This cause a fault exception when you step into the next instruction as it means you are trying to execute an ARM instruction.

    regards,
    Joseph
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