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Flags of APSR Register in Cortex M3

Muhammad Ahsan
Note: This was originally posted on 19th April 2011 at http://forums.arm.com

Hello all,
I am having probelm in writing Flags of APSR Register in Cortex M3. The result of a comparison cuases the negative flag to get set to 1. Next instruction reads the APSR using MRS instruction. Before executing this instruction I clear the negative flag to 0. If I execute the instruction of reading the APSR after clearing the negative flag, program jumps to hardfault handler. Reference manual states that these flags are writable.
We can write APSR using MSR instruction too. But is it possible to change a single bit(Flag) as I have mentioned above?
Thanks in advance
Parents
  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    How do you clear the APSR? By a debugger?
    Yes I do so using Debugger. I am using IAR Tool chain and here I have possibility to view all registers including APSR and writable bits can be changed to 0 or 1. There is another T bit in EPSR register which defines ARM mode when written to 0 and for Thumb mode it has to be written to 1. I am not touching this bit at all. All I do it to chnage the state of flag in APSR from 1 to 0 and vice versa. the program hits hardfault exception for all flags no matter the flag is changed from 0 to 1 or 1 to 0.
Reply
  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    How do you clear the APSR? By a debugger?
    Yes I do so using Debugger. I am using IAR Tool chain and here I have possibility to view all registers including APSR and writable bits can be changed to 0 or 1. There is another T bit in EPSR register which defines ARM mode when written to 0 and for Thumb mode it has to be written to 1. I am not touching this bit at all. All I do it to chnage the state of flag in APSR from 1 to 0 and vice versa. the program hits hardfault exception for all flags no matter the flag is changed from 0 to 1 or 1 to 0.
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