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instruction cycle timing & dual issue in Cortex A8

Note: This was originally posted on 8th April 2011 at http://forums.arm.com

Hi, I'm trying to really understand the instruction cycle timing and dual-issue interactions in ARM Cortex-A8. Having spent quite a few hours on this, I have a feeling that this aspect is not explained in ARM technical reference manuals. So, here is my question with respect to the following snippet taken straight from the manual (section 16.3, Table 16-15 Dual-issue restrictions):

Data source hazard
----------------------------
ADD r1, r2, r3         1         -
ADD r4, r1, r6         2        Wait for r1
LDR r7, [r4]             4        Wait two cycles for r4

I think LDR must be issued in the third cycle and not in the fourth cycle because the second ADD instruction would yield R4 by the end of cycle 2.

And BTW I have tried http://www.avison.me.uk/ben/programming/cortex-a8.html before reaching here

thanks!
devi prasad

barney vardanyan over 12 years ago

Note: This was originally posted on 12th April 2011 at http://forums.arm.com

http://forums.arm.co...n-cycle-timing/

here is many usefull information about cycle timing)
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Etienne SOBOLE over 12 years ago

Note: This was originally posted on 8th April 2011 at http://forums.arm.com

Interesting.

You help me to find an interesting bug
Well you can use the cycle counter
http://pulsar.webshaker.net/ccc/index.php

But the answer to your question is:
- ADD publish it's result (r4) in the end of stage 2
- LDR need r4 in the beginning of stage 1

You can suppose that end of stage 2 is the same thing as beginnig of stage 3
So 3 - 1 = 2 cycle between your ADD and your LDR.
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instruction cycle timing &#38; dual issue in Cortex A8

instruction cycle timing & dual issue in Cortex A8