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Non-Temporal Writes in SIMD Instruction set

Jeff Kirkham
Note: This was originally posted on 21st March 2011 at http://forums.arm.com

X-86 platform supports what they term as non-temporal writes. This just means stores from the registers to memory that do not influence the cache. They are purported to run faster. Are there similar instructions for the NEON where we can speed up a simple memory copy by writing directly to memory and bypassing the cache?
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  • Arm Employee Badge
    Note: This was originally posted on 22nd March 2011 at http://forums.arm.com

    No, ARM does not have these types of instruction. The only direct programmer control of memory cacheability is via the page tables.

    However, do you have any numbers to suggest that writing to uncached buffered memory is any faster than writing to cached memory on ARM? Most recent ARM cores optimize caches for memcpy performance, as it is a pretty common use case.

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  • Arm Employee Badge
    Note: This was originally posted on 22nd March 2011 at http://forums.arm.com

    No, ARM does not have these types of instruction. The only direct programmer control of memory cacheability is via the page tables.

    However, do you have any numbers to suggest that writing to uncached buffered memory is any faster than writing to cached memory on ARM? Most recent ARM cores optimize caches for memcpy performance, as it is a pretty common use case.

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