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Problem disabling cache on ARM926ej-s

aleksa
Parents
  • Note: This was originally posted on 17th March 2011 at http://forums.arm.com

    Or maybe like this (please answer)






    disablecache:    mov r0,#0                 @ drain write buffer
               mcr p15, 0, r0, c7, c10, 4

               mrc p15, 0, r15, c7, c14, 3  @ test, clean and invalidate
               bne disablecache

    @@@@            mcr p15, 0, r0, c7, c6, 0    @ invalidate dcache

               mrc p15, 0, r0, c1, c0, 0    @ Disable Icache(12), Dcache(2) and MMU(0)
               bic r0, r0, #4096
               bic r0, r0, #5
               mcr p15, 0, r0, c1, c0, 0

               mov pc,lr                 @ return to SWI handler







    What about those NOPs or delays I see in some sources after accessing CP15?

Reply
  • Note: This was originally posted on 17th March 2011 at http://forums.arm.com

    Or maybe like this (please answer)






    disablecache:    mov r0,#0                 @ drain write buffer
               mcr p15, 0, r0, c7, c10, 4

               mrc p15, 0, r15, c7, c14, 3  @ test, clean and invalidate
               bne disablecache

    @@@@            mcr p15, 0, r0, c7, c6, 0    @ invalidate dcache

               mrc p15, 0, r0, c1, c0, 0    @ Disable Icache(12), Dcache(2) and MMU(0)
               bic r0, r0, #4096
               bic r0, r0, #5
               mcr p15, 0, r0, c1, c0, 0

               mov pc,lr                 @ return to SWI handler







    What about those NOPs or delays I see in some sources after accessing CP15?

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