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Who controls HREADY in AHB?

Note: This was originally posted on 5th March 2011 at http://forums.arm.com

Q1: Who controls HREADY in AHB?In FAQ, it is said: "General: Is HREADY an input or an output from slaves?
Applies to: AHB
An AHB slave must have the HREADY signal as both an input and an output.
HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.
HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.
Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input."

Does it mean that it is slave that controls the HREADY?

If it is, if a master writes data into a slave, how can the slave know when the transmission is completed? that is to say, when to set HREADY to high or low?

Thanks a lot.

Jerry Feng over 12 years ago

Note: This was originally posted on 6th March 2011 at http://forums.arm.com

Thank you very much.
I have another question when reading the spec.
It is said that HGRANTx "This signal indicates that bus master x is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADY is HIGH, so a master gets access to the bus when both HREADY and HGRANTx are HIGH."

My question is : "How can I know the transfer is about to end?"
I cannot judge it by HREADY since HREADY would be high all time for a write transaction.

for example, for Fig.3-17, it is said that "The arbiter changes the HGRANTx signals when the penultimate (one before last) address has been sampled. "
Does it mean that I need a counter (for example) in Arbiter to count the number, and when counting to the penultimate, the arbiter can change the HGRANTx?

Thanks a lot
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Jerry Feng over 12 years ago

Note: This was originally posted on 6th March 2011 at http://forums.arm.com

For example, when master 1 is writing 320 bytes to slave 1, the arbiter changes HGRANT1 to HGRANT2 when master1 only writes 160bytes,

since HREADY is high on each valid data cycle,
does it mean that master1 has to handover the control to master 2 even he does not complete the transaction?

Thanks a lot.
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Simon Craske over 12 years ago

Note: This was originally posted on 5th March 2011 at http://forums.arm.com

The currently active slave is in control of the HREADY.
For a write transaction, the master must provide (the same) valid HWDATA on every single cycle until HREADY is high.

hth
s.
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