This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Is there ANY Cortex core that supports reentrant interrupts?

Note: This was originally posted on 28th February 2011 at http://forums.arm.com

For some (external to me) reason I am stuck with the Cortex but trying to find work around to my software issues with the lack of reentrant interrupts in CM3. Does CM4 support reentrancy? Or maybe CM0? Anything at all?
Please help!

Parents

Simon Craske over 12 years ago

Note: This was originally posted on 7th March 2011 at http://forums.arm.com

This is a thought experiment rather than tested code, but you could try something like:

int_handler PUSH {r4,lr} ;// Preserve EXC_RETURN (and SP align) LDR r0,=thread_exit ;// Thread LR must generate an exit LDR r1,=int_code ;// Thread PC is our real handler LDR r2,=0x01000000 ;// PSR for thread in Thumb-state PUSH {r0-r2} ;// Create LR, PC and PSR SUB sp,sp,#(5*4) ;// Allocate space for r0-r3 and r12 LDR r0,=0xFFFFFFF9 ;// Thread using MSP return BX r0 ;// Return to newly created thread svc_handler ADD sp,sp,#(9*4) ;// Remove Thread and r4 from stack POP {pc} ;// Perform standard exception return thread_exit SVC 0 ;// Return to handler mode int_code .... boot_code LDR r1,=0xE000ED14 ;// CCR register address LDR r0,[r1] ORR r0,r0,#1 ;// Enable NONBASETHRDENA STR r0,[r1] ....
The short int_handler creates an exception stack frame for a new thread to actually run the re-entrant interrupt handler (int_code in the example).
By returning, the int_handler automatically re-enables its interrupt for preemption, thus permitting re-entrancy.
Exiting from the int_code routine requires entry back to handler mode (performed via setting the LR to point to an SVC in the example above), which then strips the thread from the stack frame, and returns as though the original interrupt handler would have done.
Note that to make this behave properly, the handler used for exiting (SVCall in this case) needs to have the same or higher priority than the triggering interrupt.
The example assumes that the source is a pulse interrupt, if this isn't the case, then int_handler would also need to clear the source before starting the thread.
There are various other optimisations you could do, for example using the same interrupt for entry and exit by using software triggered interrupts etc.

hth
s.
Cancel
Vote up 0 Vote down

Cancel

Reply

Simon Craske over 12 years ago

Note: This was originally posted on 7th March 2011 at http://forums.arm.com

This is a thought experiment rather than tested code, but you could try something like:

int_handler PUSH {r4,lr} ;// Preserve EXC_RETURN (and SP align) LDR r0,=thread_exit ;// Thread LR must generate an exit LDR r1,=int_code ;// Thread PC is our real handler LDR r2,=0x01000000 ;// PSR for thread in Thumb-state PUSH {r0-r2} ;// Create LR, PC and PSR SUB sp,sp,#(5*4) ;// Allocate space for r0-r3 and r12 LDR r0,=0xFFFFFFF9 ;// Thread using MSP return BX r0 ;// Return to newly created thread svc_handler ADD sp,sp,#(9*4) ;// Remove Thread and r4 from stack POP {pc} ;// Perform standard exception return thread_exit SVC 0 ;// Return to handler mode int_code .... boot_code LDR r1,=0xE000ED14 ;// CCR register address LDR r0,[r1] ORR r0,r0,#1 ;// Enable NONBASETHRDENA STR r0,[r1] ....
The short int_handler creates an exception stack frame for a new thread to actually run the re-entrant interrupt handler (int_code in the example).
By returning, the int_handler automatically re-enables its interrupt for preemption, thus permitting re-entrancy.
Exiting from the int_code routine requires entry back to handler mode (performed via setting the LR to point to an SVC in the example above), which then strips the thread from the stack frame, and returns as though the original interrupt handler would have done.
Note that to make this behave properly, the handler used for exiting (SVCall in this case) needs to have the same or higher priority than the triggering interrupt.
The example assumes that the source is a pulse interrupt, if this isn't the case, then int_handler would also need to clear the source before starting the thread.
There are various other optimisations you could do, for example using the same interrupt for entry and exit by using software triggered interrupts etc.

hth
s.
Cancel
Vote up 0 Vote down

Cancel

Children

No data