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Is there ANY Cortex core that supports reentrant interrupts?

Konstantin Dimitrov
Note: This was originally posted on 28th February 2011 at http://forums.arm.com

For some (external to me) reason I am stuck with the Cortex but trying to find work around to my software issues with the lack of reentrant interrupts in CM3. Does CM4 support reentrancy? Or maybe CM0? Anything at all?
Please help!


Parents
  • Arm Employee Badge
    Note: This was originally posted on 2nd March 2011 at http://forums.arm.com

    It is possible to use re-entrant interrupts on Cortex-M3/4 using the non-base-thread feature. You simply need to enable NONBASETHRDENA, and have the interrupt create a stack frame to run the body of the handler and perform a return using it,  thus removing the interrupt from the active list, and therefore lowering the core's priority such that the same interrupt can be taken again.

    hth
    s.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 2nd March 2011 at http://forums.arm.com

    It is possible to use re-entrant interrupts on Cortex-M3/4 using the non-base-thread feature. You simply need to enable NONBASETHRDENA, and have the interrupt create a stack frame to run the body of the handler and perform a return using it,  thus removing the interrupt from the active list, and therefore lowering the core's priority such that the same interrupt can be taken again.

    hth
    s.
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