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Is there ANY Cortex core that supports reentrant interrupts?

Konstantin Dimitrov
Note: This was originally posted on 28th February 2011 at http://forums.arm.com

For some (external to me) reason I am stuck with the Cortex but trying to find work around to my software issues with the lack of reentrant interrupts in CM3. Does CM4 support reentrancy? Or maybe CM0? Anything at all?
Please help!


Parents
  • Note: This was originally posted on 7th March 2011 at http://forums.arm.com

    Sim, can you please help me out just a little bit more? I tried your example and it generates a HardFault exception after exiting my re-entrant function for the first time. Here is my test code which is basically a copy-paste of yours (I use Rowley Crossworks if that is of any importance). I've set the NONBASETHRDENA bit outside in my initialisation code: SCB_CCR|=SCB_CCR_NONBASETHRDENA;
    When I trace the exception occurs upon the execution of POP {PC}, which prompts my thoughts that the stack is maybe not right set up for the exit. However I really don't know and rely on your comments for this.
    Thank you!


    void SysCall(void) {

        LED^=1;  // just for the test

        __asm("thread_exit:");
        __asm("SVC 0");                 // return to handler mode
    }

    void SysTick_Handler(void) __attribute__ ((naked));
    void SysTick_Handler(void) {
        __asm("PUSH {r4,lr}");          // preserve EXC_RETURN (and SP align)
        __asm("LDR r0,=thread_exit");   // thread LR must generate an exit
        __asm("LDR r1,=SysCall");       // thread PC is our real handler
        __asm("LDR r2,=0x01000000");    // PSR for thread in Thumb-state
        __asm("PUSH {r0-r2}");          // create LR, PC and PSR
        __asm("SUB sp,sp,#(5*4)");      // allocate space for r0-r3 and r12
        __asm("LDR r0,=0xFFFFFFF9");    // thread using MSP return
        __asm("BX r0");                 // return to newly created thread
    }

    void SVC_Handler(void) __attribute__ ((naked));
    void SVC_Handler(void) {
        __asm("ADD sp,sp,#(9*4)");      // remove thread and r4 from stack
        __asm("POP {pc}");              // perform standard exception return
    }
Reply
  • Note: This was originally posted on 7th March 2011 at http://forums.arm.com

    Sim, can you please help me out just a little bit more? I tried your example and it generates a HardFault exception after exiting my re-entrant function for the first time. Here is my test code which is basically a copy-paste of yours (I use Rowley Crossworks if that is of any importance). I've set the NONBASETHRDENA bit outside in my initialisation code: SCB_CCR|=SCB_CCR_NONBASETHRDENA;
    When I trace the exception occurs upon the execution of POP {PC}, which prompts my thoughts that the stack is maybe not right set up for the exit. However I really don't know and rely on your comments for this.
    Thank you!


    void SysCall(void) {

        LED^=1;  // just for the test

        __asm("thread_exit:");
        __asm("SVC 0");                 // return to handler mode
    }

    void SysTick_Handler(void) __attribute__ ((naked));
    void SysTick_Handler(void) {
        __asm("PUSH {r4,lr}");          // preserve EXC_RETURN (and SP align)
        __asm("LDR r0,=thread_exit");   // thread LR must generate an exit
        __asm("LDR r1,=SysCall");       // thread PC is our real handler
        __asm("LDR r2,=0x01000000");    // PSR for thread in Thumb-state
        __asm("PUSH {r0-r2}");          // create LR, PC and PSR
        __asm("SUB sp,sp,#(5*4)");      // allocate space for r0-r3 and r12
        __asm("LDR r0,=0xFFFFFFF9");    // thread using MSP return
        __asm("BX r0");                 // return to newly created thread
    }

    void SVC_Handler(void) __attribute__ ((naked));
    void SVC_Handler(void) {
        __asm("ADD sp,sp,#(9*4)");      // remove thread and r4 from stack
        __asm("POP {pc}");              // perform standard exception return
    }
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