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I-cache coherency maintence

Vladimir Murzin
Note: This was originally posted on 14th February 2011 at http://forums.arm.com

I'm a newbie in ARM.
It's said that in case of multi-core I-cache coherency not maintained by SCU even if memory marked as sharable.
I've got some self-modifying code  and I wonder which steps  should I do to maintain I-cache coherency?

Thanks.
  • Note: This was originally posted on 15th February 2011 at http://forums.arm.com


    ARM processors have traditionally not provided automatic coherency management between the I and D sides.  So self-modifying code (and similar) has always required manual cache maintenance. 

    You will first need to clean the d cache, and then invalidate the I side.

    You don't say which processor you're using.  If it's the A9 or A5, they have the option of having cache maintenance broadcasting.  This is when doing the operation on any one CPU causes the other CPUs to also perform the operation.  It requires support to be enabled on each CPU (FW bit in ACTLR) and for you to use the inner shareable versions of the i side operations.


    It's cortex A-9 under Linux.
    I wonder if could I use DMB, DSB and ISB instructions to perform cache maintenance? If not, which functions from libc should I use? Might be there is article or how-to for newbies where described this question?

    Thank you.
  • Note: This was originally posted on 21st February 2011 at http://forums.arm.com

    Thank you for clarification!
  • Arm Employee Badge
    Note: This was originally posted on 14th February 2011 at http://forums.arm.com

    ARM processors have traditionally not provided automatic coherency management between the I and D sides.  So self-modifying code (and similar) has always required manual cache maintenance. 

    You will first need to clean the d cache, and then invalidate the I side.

    You don't say which processor you're using.  If it's the A9 or A5, they have the option of having cache maintenance broadcasting.  This is when doing the operation on any one CPU causes the other CPUs to also perform the operation.  It requires support to be enabled on each CPU (FW bit in ACTLR) and for you to use the inner shareable versions of the i side operations.
  • Arm Employee Badge
    Note: This was originally posted on 15th February 2011 at http://forums.arm.com

    You can't do this from userspace - you don't have enough privilege to perform cache operations. You will need a simple kernel driver to perform this task for you.