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cycle penality before using a register as pointer

Etienne SOBOLE
Note: This was originally posted on 28th January 2011 at http://forums.arm.com

Hi.

it seem's that you can't use a modified register as a load address directly in the next cycle (with the Cortex A8)


For example

ADD   r0, r0, #16
LDR   r1,[r0]


will not execute in 2 cycles but in 3 cycles.
I'm looking in the ARM documentation where this penality cycle is explain but I do not find !!!

If I simply use the cortex A8 cycle table:
ADD will write his result in E2
while LDR will need R0 in E1

So If I just apply those rules, the 2 instructions should execute in 2 cycles.

So !!! Does anybody can tell me where this pipeline-dependent latency is explain (or simply notify) ?

Thank's
Parents
  • Arm Employee Badge
    Note: This was originally posted on 28th January 2011 at http://forums.arm.com

    How are you measuring the 3 cycles?

    ... also be aware that ARM make it very clear in the manual that the timing tables for Cortex-A8 are only approximations. From the TRM:


    This chapter provides the information to estimate how much execution time particular code sequences require. The complexity of the processor makes it impossible to guarantee precise timing information with hand calculations.
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  • Arm Employee Badge
    Note: This was originally posted on 28th January 2011 at http://forums.arm.com

    How are you measuring the 3 cycles?

    ... also be aware that ARM make it very clear in the manual that the timing tables for Cortex-A8 are only approximations. From the TRM:


    This chapter provides the information to estimate how much execution time particular code sequences require. The complexity of the processor makes it impossible to guarantee precise timing information with hand calculations.
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