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cycle penality before using a register as pointer

Etienne SOBOLE
Note: This was originally posted on 28th January 2011 at http://forums.arm.com

Hi.

it seem's that you can't use a modified register as a load address directly in the next cycle (with the Cortex A8)


For example

ADD   r0, r0, #16
LDR   r1,[r0]


will not execute in 2 cycles but in 3 cycles.
I'm looking in the ARM documentation where this penality cycle is explain but I do not find !!!

If I simply use the cortex A8 cycle table:
ADD will write his result in E2
while LDR will need R0 in E1

So If I just apply those rules, the 2 instructions should execute in 2 cycles.

So !!! Does anybody can tell me where this pipeline-dependent latency is explain (or simply notify) ?

Thank's
Parents
  • Note: This was originally posted on 28th January 2011 at http://forums.arm.com

    Ok.

    I'm back, and this time I'm a little bit more sure about my purpose...

    This code take 3 cycles

    LDR   r0, [r8]
    ADD   r1, r1, r0


    LDR give is result in E3
    ADD need r0 in E2

    So this code should take 2 cycles




    LDR   r0, [r8]
    MOV   r1, r0


    take 4 cycles while MOV need r0 in E1 !
    It should take 3 cycles !!!

    Why ???
    I do not find case where those code take correct cycles.
    It give more correct result if I say LDR give is result in E4 !
Reply
  • Note: This was originally posted on 28th January 2011 at http://forums.arm.com

    Ok.

    I'm back, and this time I'm a little bit more sure about my purpose...

    This code take 3 cycles

    LDR   r0, [r8]
    ADD   r1, r1, r0


    LDR give is result in E3
    ADD need r0 in E2

    So this code should take 2 cycles




    LDR   r0, [r8]
    MOV   r1, r0


    take 4 cycles while MOV need r0 in E1 !
    It should take 3 cycles !!!

    Why ???
    I do not find case where those code take correct cycles.
    It give more correct result if I say LDR give is result in E4 !
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