This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

cycle penality before using a register as pointer

Note: This was originally posted on 28th January 2011 at http://forums.arm.com

Hi.

it seem's that you can't use a modified register as a load address directly in the next cycle (with the Cortex A8)


For example

ADD   r0, r0, #16
LDR   r1,[r0]

will not execute in 2 cycles but in 3 cycles.
I'm looking in the ARM documentation where this penality cycle is explain but I do not find !!!

If I simply use the cortex A8 cycle table:
ADD will write his result in E2
while LDR will need R0 in E1

So If I just apply those rules, the 2 instructions should execute in 2 cycles.

So !!! Does anybody can tell me where this pipeline-dependent latency is explain (or simply notify) ?

Thank's

Parents

Etienne SOBOLE over 12 years ago

Note: This was originally posted on 28th January 2011 at http://forums.arm.com

Yes isogen...
You're right, it finally take 2 cycles.

First of all.
I found an example here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babhefaj.html
the 5th example "Data source hazard" let think that there were a penality cycle.

After that I found this information on Internet too.

Finally, I've made a small test which was wrong.

But.
In fact, you're right, there is not a such latency !
Sorry.

I think, that except for memory delai cycle, it should be possible to count correct cycles (in most case).
Cancel
Vote up 0 Vote down

Cancel

Reply

Etienne SOBOLE over 12 years ago

Note: This was originally posted on 28th January 2011 at http://forums.arm.com

Yes isogen...
You're right, it finally take 2 cycles.

First of all.
I found an example here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babhefaj.html
the 5th example "Data source hazard" let think that there were a penality cycle.

After that I found this information on Internet too.

Finally, I've made a small test which was wrong.

But.
In fact, you're right, there is not a such latency !
Sorry.

I think, that except for memory delai cycle, it should be possible to count correct cycles (in most case).
Cancel
Vote up 0 Vote down

Cancel

Children

No data