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AXI ID problem for cascaded interconnect design

Nan Kou
Note: This was originally posted on 18th December 2010 at http://forums.arm.com

As we know, the interconnect can add bits  to ID fields to indentify the master issuing the transaction.  In the SoC design, it is common that  cascaded interconnects , like hierarchical architecture, compose the interconnect network. for that  the ID width of the master interface of the cascaded design would be extended to many bits, however, some slave cannot support too many ID bits. Is there any recommendations or discussions about handling this problem? Hope for your kind help:)





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  • Arm Employee Badge
    Note: This was originally posted on 21st December 2010 at http://forums.arm.com

    If there is no way of reducing the number of active ID bits seen at a slave (i.e. looking at all the potential ID encodings that could physical reach this slave might highlight a few bits that remain static, and so could be tied off or left unconnected), then you will need to implement some sort of ID compression logic.

    This compression logic would perhaps need to contain a memory of "interconnect ID" width and "slave combined acceptance capability" depth, and this memory will store the real ID value for a transaction, and will generate a narrower ID value (width determined by the acceptance capability of the slave) for the slave to use, expanding the ID back to the original value for the RID and BID returns.

    The logic is not simple because there are AXI ordering issues to take into account, and issues for exclusive accesses, but it would then reduce the number of ID bits needed at the slave if it has been designed (incorrectly) to not have a configurable ID width.

    That is how I'd think you would need to attack this problem.

    JD
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  • Arm Employee Badge
    Note: This was originally posted on 21st December 2010 at http://forums.arm.com

    If there is no way of reducing the number of active ID bits seen at a slave (i.e. looking at all the potential ID encodings that could physical reach this slave might highlight a few bits that remain static, and so could be tied off or left unconnected), then you will need to implement some sort of ID compression logic.

    This compression logic would perhaps need to contain a memory of "interconnect ID" width and "slave combined acceptance capability" depth, and this memory will store the real ID value for a transaction, and will generate a narrower ID value (width determined by the acceptance capability of the slave) for the slave to use, expanding the ID back to the original value for the RID and BID returns.

    The logic is not simple because there are AXI ordering issues to take into account, and issues for exclusive accesses, but it would then reduce the number of ID bits needed at the slave if it has been designed (incorrectly) to not have a configurable ID width.

    That is how I'd think you would need to attack this problem.

    JD
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