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AXI ID problem for cascaded interconnect design

Note: This was originally posted on 18th December 2010 at http://forums.arm.com

As we know, the interconnect can add bits to ID fields to indentify the master issuing the transaction. In the SoC design, it is common that cascaded interconnects , like hierarchical architecture, compose the interconnect network. for that the ID width of the master interface of the cascaded design would be extended to many bits, however, some slave cannot support too many ID bits. Is there any recommendations or discussions about handling this problem? Hope for your kind help:)

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Nan Kou over 12 years ago

Note: This was originally posted on 27th December 2010 at http://forums.arm.com

It helps. Thanks for JD's kind and patient reply every time.
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Nan Kou over 12 years ago

Note: This was originally posted on 27th December 2010 at http://forums.arm.com

It helps. Thanks for JD's kind and patient reply every time.
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