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Duplicate globally-mapped Micro TLB entries

Christoffer Dall
Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

I am mapping a page using the same virtual address with the same properties in two separate page tables, which are accessed using two separate ASIDs.

Even though the page is mapped as a global page, I am seeing two valid entries in both the instruction and data Micro TLB. If I read the specification documents correctly, this is not supposed to happen using global mappings.

I would very much like to know if I have a software bug or this is indeed the intended hardware behavior. The information below is gathered using the CP15 TLB Debug registers and the TLB Match and Load operations were disabled before collecting this information.

Data Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
2:  ffff120c  x    12  161ee3b6  000001ee
3:  ffff120b  x    11  161ee3b6  000001ee
4:  ffff120b  x    11  161ee3b7  000001ee


Instr. Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
0:  ffff120c  x    12  161ee3b6  000001ee
1:  ffff120b  x    11  161ee3b7  000001ee
3:  ffff120c  x    12  161ee3b6  000001ee


Instr. Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
17:  ffff120b  x    11  161ee3b7  0a0001ee


Thanks!

-Christoffer
Parents
  • Arm Employee Badge
    Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

    Given that the finest granularity of an MMU page is 4KB (or 1KB if you are on an ARMv5 core), and in either case the bottom 12 or 10 bits of the VA and the PA must match, it seems strange that you have addresses which are not 1KB or 4KB aligned, and in no case have bottom bits which match.

    So, your data looks wrong to me. How are you taking these measurements, and on what platform?
Reply
  • Arm Employee Badge
    Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

    Given that the finest granularity of an MMU page is 4KB (or 1KB if you are on an ARMv5 core), and in either case the bottom 12 or 10 bits of the VA and the PA must match, it seems strange that you have addresses which are not 1KB or 4KB aligned, and in no case have bottom bits which match.

    So, your data looks wrong to me. How are you taking these measurements, and on what platform?
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