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Duplicate globally-mapped Micro TLB entries

Christoffer Dall
Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

I am mapping a page using the same virtual address with the same properties in two separate page tables, which are accessed using two separate ASIDs.

Even though the page is mapped as a global page, I am seeing two valid entries in both the instruction and data Micro TLB. If I read the specification documents correctly, this is not supposed to happen using global mappings.

I would very much like to know if I have a software bug or this is indeed the intended hardware behavior. The information below is gathered using the CP15 TLB Debug registers and the TLB Match and Load operations were disabled before collecting this information.

Data Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
2:  ffff120c  x    12  161ee3b6  000001ee
3:  ffff120b  x    11  161ee3b6  000001ee
4:  ffff120b  x    11  161ee3b7  000001ee


Instr. Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
0:  ffff120c  x    12  161ee3b6  000001ee
1:  ffff120b  x    11  161ee3b7  000001ee
3:  ffff120c  x    12  161ee3b6  000001ee


Instr. Micro TLB:

idx  VA        G  ASID  PA        ATTR
---  --------  -  ----  --------  --------
17:  ffff120b  x    11  161ee3b7  0a0001ee


Thanks!

-Christoffer
Parents
  • Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

    The measurements are taken using the TLB VA, PA and Attribute registers in CP15. The system is an arm1136 (specifically an HTC Dream device with an MSM 7200 series core.

    ARM DDI 0211K (see pages 3-196 to 3-209) specifies the formats of those registers, and specifically for the VA, the format is that bits [31:10] give you the address and bit 9 is set for global entries and clear for non-global - in the latter case bits [7:0] gives the ASID.

    The G (global) and ASID columns are just extracted bits from the VA column.

    Equally, the PA field contains the AP and valid bits amongst others in the least significant bits.

    The pages under 0xffff are all 4KB small pages.

    Thanks.
Reply
  • Note: This was originally posted on 3rd November 2010 at http://forums.arm.com

    The measurements are taken using the TLB VA, PA and Attribute registers in CP15. The system is an arm1136 (specifically an HTC Dream device with an MSM 7200 series core.

    ARM DDI 0211K (see pages 3-196 to 3-209) specifies the formats of those registers, and specifically for the VA, the format is that bits [31:10] give you the address and bit 9 is set for global entries and clear for non-global - in the latter case bits [7:0] gives the ASID.

    The G (global) and ASID columns are just extracted bits from the VA column.

    Equally, the PA field contains the AP and valid bits amongst others in the least significant bits.

    The pages under 0xffff are all 4KB small pages.

    Thanks.
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