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[ARM926EJS] improve write miss

stanley shih
Note: This was originally posted on 5th October 2010 at http://forums.arm.com

Hello experts,

    The platform I am using is ARM926EJS. Cache policy is write-back and only read-allocate.
    From the profile result, the program I want to optimize has too many write misses (write buffer refill)
    Can anyone give me some guidelines or tricks to improve my program? thanks.

BR,
Stanley
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  • Arm Employee Badge
    Note: This was originally posted on 11th October 2010 at http://forums.arm.com

    > Will STM make all store write to the same write buffer entry?
    The [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/I31031.html"]write buffer on the 926[/url] can queue up 16 data words at 4 addresses. An STR (or STRH or STRB) that misses the cache (or is uncacheable) will use one data word and one address.  An STM of N registers will use N data words and one address.

    Depending on your memory system, there may also be some benefit to using STM of 4 or 8 registers since that will allow the 926 to use [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/Cacjgjec.html"]bursts on  the external AHB bus[/url].

    > Does write order affect the performance if the data in the cache or not in the cache?
    I think I'm going to retract my "consecutive ascending addresses" comment.  I was imagining a difference between consecutive ascending addresses and consecutive decending addresses, but I'm not sure it makes any difference, especially without write allocate (and maybe even with).  For writes that miss the cache, except for the STM comments above, I don't think it will make any difference on the 926 (since it's not merging writes).
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  • Arm Employee Badge
    Note: This was originally posted on 11th October 2010 at http://forums.arm.com

    > Will STM make all store write to the same write buffer entry?
    The [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/I31031.html"]write buffer on the 926[/url] can queue up 16 data words at 4 addresses. An STR (or STRH or STRB) that misses the cache (or is uncacheable) will use one data word and one address.  An STM of N registers will use N data words and one address.

    Depending on your memory system, there may also be some benefit to using STM of 4 or 8 registers since that will allow the 926 to use [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/Cacjgjec.html"]bursts on  the external AHB bus[/url].

    > Does write order affect the performance if the data in the cache or not in the cache?
    I think I'm going to retract my "consecutive ascending addresses" comment.  I was imagining a difference between consecutive ascending addresses and consecutive decending addresses, but I'm not sure it makes any difference, especially without write allocate (and maybe even with).  For writes that miss the cache, except for the STM comments above, I don't think it will make any difference on the 926 (since it's not merging writes).
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